公开(公告)号：US08927384B2

公开(公告)日：2015-01-06

申请号：US13400993

申请日：2012-02-21

Applicant: Jong-Kyu Kim ,  Sangsup Jeong ,  Kukhan Yoon ,  Junsoo Lee ,  SungII Cho ,  Yong-Joon Choi

Inventor： Jong-Kyu Kim ,  Sangsup Jeong ,  Kukhan Yoon ,  Junsoo Lee ,  SungII Cho ,  Yong-Joon Choi

IPC: H01L21/20 ,  H01L27/108 ,  H01L49/02 ,  H01L27/02 ,  H01L21/311

CPC classification number: H01L28/91 ,  H01L21/31144 ,  H01L27/0203 ,  H01L27/10817 ,  H01L27/10852

Abstract: A method of fabricating a semiconductor memory device includes forming a hard mask pattern using a damascene method on a lower mold layer stacked on a substrate and etching the lower mold layer using the hard mask pattern as an etch mask to define a protrusion under the hard mask pattern. A support pattern is formed on a top surface of the etched lower mold layer, the top surface of the etched lower mold layer being located at a lower level than a top surface of the protrusion. A lower electrode supported by the support pattern is formed.

Abstract translation: 一种制造半导体存储器件的方法包括：使用镶嵌方法在堆叠在衬底上的下模层上形成硬掩模图案，并使用硬掩模图案蚀刻下模层作为蚀刻掩模，以在硬掩模之下限定突起 模式。 在蚀刻的下模层的顶表面上形成支撑图案，蚀刻的下模层的顶表面位于比突起的顶表面更低的水平。 形成由支撑图案支撑的下电极。

公开(公告)号：US20120225530A1

公开(公告)日：2012-09-06

申请号：US13400993

申请日：2012-02-21

Applicant: Jong-Kyu KIM ,  Sangsup Jeong ,  Kukhan Yoon ,  Junsoo Lee ,  SungII Cho ,  Yong-Joon Choi

Inventor： Jong-Kyu KIM ,  Sangsup Jeong ,  Kukhan Yoon ,  Junsoo Lee ,  SungII Cho ,  Yong-Joon Choi

IPC: H01L21/02 ,  H01L21/768

CPC classification number: H01L28/91 ,  H01L21/31144 ,  H01L27/0203 ,  H01L27/10817 ,  H01L27/10852

Abstract: A method of fabricating a semiconductor memory device includes forming a hard mask pattern using a damascene method on a lower mold layer stacked on a substrate and etching the lower mold layer using the hard mask pattern as an etch mask to define a protrusion under the hard mask pattern. A support pattern is formed on a top surface of the etched lower mold layer, the top surface of the etched lower mold layer being located at a lower level than a top surface of the protrusion. A lower electrode supported by the support pattern is formed.

Abstract translation: 一种制造半导体存储器件的方法包括：使用镶嵌方法在堆叠在衬底上的下模层上形成硬掩模图案，并使用硬掩模图案蚀刻下模层作为蚀刻掩模，以在硬掩模之下限定突起 模式。 在蚀刻的下模层的顶表面上形成支撑图案，蚀刻的下模层的顶表面位于比突起的顶表面更低的水平。 形成由支撑图案支撑的下电极。