公开(公告)号：US5994206A

公开(公告)日：1999-11-30

申请号：US944170

申请日：1997-10-06

申请人： Subhash Gupta ,  Susan Hsuching Chen

发明人： Subhash Gupta ,  Susan Hsuching Chen

IPC分类号： H01L21/768 ,  H01L21/225 ,  H01L21/385

CPC分类号： H01L21/76877 ,  H01L21/76802

摘要： A method and system for providing a via structure for a high conductivity metal of a integrated circuit is disclosed. In a first aspect the method and system comprises etching a photoresist material and a dielectric material down to the high conductivity metal to form a via hole. The via hole includes sputtered high conductivity metal on the sidewalls. The method and system further includes providing a via plug material within the via hole. The vial plug material substantially covers a base portion of the high conductivity metal and the sidewalls of the via hole. The via plug material is also capable of gettering or dissolving the high conductivity metal sputtered on the sidewalls of the dielectric material. In a second aspect, a via structure for an integrated circuit is disclosed in accordance with the present invention. The via structure includes a high conductivity metal and a dielectric material surrounding the high conductivity metal. The dielectric material includes sidewalls to form a via hole on tope of the high conductivity metal. The via structure further includes a via plug material covering the high conductivity metal and substantially filling the via hole. The via plug material is also capable of gettering or dissolving the high conductivity metal sputtered on the sidewalls of the via hole. Accordingly, by providing a via plug material within the via hole, the via plug material getters or dissolves the high conductivity metal that reaches the sidewalls of the dielectric layer during the via etch and sputter etch processes and the junction poisoning problems associated therewith are substantially minimized.

摘要翻译： 公开了一种用于为集成电路的高导电性金属提供通孔结构的方法和系统。 在第一方面，该方法和系统包括将光致抗蚀剂材料和电介质材料蚀刻到高导电性金属上以形成通孔。 通孔包括在侧壁上的溅射的高导电性金属。 该方法和系统还包括在通孔内提供通孔塞材料。 小瓶插头材料基本上覆盖高导电性金属的基部和通孔的侧壁。 通孔插塞材料还能够吸收或溶解溅射在电介质材料的侧壁上的高导电性金属。 在第二方面中，根据本发明公开了一种用于集成电路的通孔结构。 通孔结构包括高导电性金属和围绕高导电性金属的介电材料。 电介质材料包括在高导电性金属的顶部上形成通孔的侧壁。 通孔结构还包括覆盖高导电性金属并基本上填充通孔的通孔塞材料。 通孔插塞材料还能够吸收或溶解溅射在通孔的侧壁上的高导电性金属。 因此，通过在通孔内提供通孔插塞材料，通孔插塞材料在通孔蚀刻和溅射蚀刻工艺期间吸收或溶解到达介电层侧壁的高导电性金属，并且与之相关的结中毒问题基本上最小化 。

公开(公告)号：US06331732B1

公开(公告)日：2001-12-18

申请号：US09439948

申请日：1999-11-12

申请人： Subhash Gupta ,  Susan Hsuching Chen

发明人： Subhash Gupta ,  Susan Hsuching Chen

IPC分类号： H01L2348

CPC分类号： H01L21/76877 ,  H01L21/76802

摘要： A method and system for providing a via structure for an integrated circuit is disclosed. The method and system includes providing a high conductivity metal that forms a metal structure consisting of the high conductivity metal. The method and system also includes a dielectric material surrounding the high conductivity metal. The dielectric material includes sidewalls to form a via hole. The method and system also include providing a via plug material other than the high conductivity metal. The via plug material covers the high conductivity metal and substantially fills the via hole. The via plug material substantially covers a base portion of the high conductivity metal and the sidewalls of the via hole. The via plug material is for gettering the high conductivity metal sputtered on the sidewalls of the via hole.

摘要翻译： 公开了一种用于提供用于集成电路的通孔结构的方法和系统。 该方法和系统包括提供形成由高导电性金属组成的金属结构的高导电性金属。 该方法和系统还包括围绕高导电性金属的电介质材料。 电介质材料包括形成通孔的侧壁。 该方法和系统还包括提供除了高导电性金属之外的通孔插塞材料。 通孔塞材料覆盖高导电性金属并且基本上填充通孔。 通孔插塞材料基本上覆盖高导电性金属的基部和通孔的侧壁。 通孔插塞材料用于吸收溅射在通孔侧壁上的高导电性金属。

公开(公告)号：US6071824A

公开(公告)日：2000-06-06

申请号：US937634

申请日：1997-09-25

申请人： Bhanwar Singh ,  Subhash Gupta ,  Mutya Vicente ,  Susan Hsuching Chen

发明人： Bhanwar Singh ,  Subhash Gupta ,  Mutya Vicente ,  Susan Hsuching Chen

IPC分类号： G03F7/09 ,  H01L21/027 ,  H01L21/3213 ,  H01L21/00

CPC分类号： H01L21/32139 ,  G03F7/091 ,  H01L21/0276

摘要： A method and system for patterning a metal layer of a semiconductor device is disclosed. The method and system includes providing a material with an antireflective low dielectric constant hard mask layer (antireflective low k hard mask layer) on top of the metal layer, and providing a photoresist pattern on top of the anti-reflective low k hard mask layer. The method and system further includes etching of the anti-reflective low k hard mask layer and etching of the metal layer, wherein the photoresist is removed but the anti-reflective low k hard mask layer remains. In a preferred embodiment, the mask layer can also be applied at low temperatures (i.e., >300.degree.) to ensure that the physical properties of the integrated circuit are not affected. Finally, the low k material does not have to be removed after processing. Accordingly, through the use of an anti-reflective low k hard mask layer, the metal patterning can be more effectively accomplished in a deep submicron process, particularly a process that is required for 0.18 microns or smaller technologies.

摘要翻译： 公开了用于图案化半导体器件的金属层的方法和系统。 该方法和系统包括在金属层的顶部提供具有抗反射低介电常数硬掩模层（抗反射低k硬掩模层）的材料，并且在抗反射低k硬掩模层的顶部提供光致抗蚀剂图案。 所述方法和系统还包括蚀刻抗反射低k硬掩模层和蚀刻金属层，其中去除光致抗蚀剂，但保留抗反射低k硬掩模层。 在优选实施例中，掩模层也可以在低温（即> 300°）下施加，以确保集成电路的物理性质不受影响。 最后，低k材料在加工后不必去除。 因此，通过使用抗反射低k硬掩模层，可以在深亚微米工艺中更有效地实现金属图案化，特别是0.18微米或更小技术所需的工艺。

公开(公告)号：US5726920A

公开(公告)日：1998-03-10

申请号：US537116

申请日：1995-09-29

申请人： Susan Hsuching Chen ,  Ying Shiau ,  Chern-Jiann Lee

发明人： Susan Hsuching Chen ,  Ying Shiau ,  Chern-Jiann Lee

IPC分类号： G01R31/28 ,  H01L21/66 ,  H01L21/304

CPC分类号： G01R31/2831 ,  G01R31/2851

摘要： In a final wafer sort (FWS) testing facility, the raw log-out data that is output by FWS test stations is augmented with additional differentiating data to thereby produce differentiable log-outs that can be sorted according to a variety of criteria including: product number or product family, time of test, specific wafer, specific production lot, intra-reticle site number, machine operator, and the specific swappable units of equipment that participated in the FWS testing. The differentiable log-outs are stored in a database and are periodically accessed by an automatic watchdog system that tests for exception conditions calling for immediate or long-term response. Corresponding alarm signals and trend reports are automatically generated and distributed to responsible personnel and/or reactive machine-systems as appropriate. The alarm distribution mechanism includes automatic paging of personnel by wireless beeper and/or e-mail. Immediate response alarms include exception conditions detected for accumulated bin counts on a per-wafer or per-lot basis. Long term alert reports include those that detect increased error rates and possible wear down of replaceable probe cards.

摘要翻译： 在最终的晶圆分类（FWS）测试设备中，由FWS测试站输出的原始注销数据将增加额外的差分数据，从而产生可分类的注销，可根据多种标准进行排序，包括：产品 数量或产品系列，测试时间，特定晶圆，特定生产批次，光标内部位置号码，机器操作员以及参与FWS测试的特定可交换设备单元。 可区分的注销存储在数据库中，并由自动看门狗系统定期访问，该系统可以测试异常情况，要求立即或长期响应。 自动生成相应的报警信号和趋势报告，并酌情分发给负责人员和/或反应性机器系统。 报警分配机制包括通过无线蜂鸣器和/或电子邮件对人员进行自动寻呼。 立即响应报警包括针对每个晶片或每批次的累积仓计数检测到的异常情况。 长期警报报告包括检测更高的探针卡的错误率增加和可能磨损的报告。