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公开(公告)号：US20250063827A1
公开(公告)日：2025-02-20
申请号：US18940498
申请日：2024-11-07
Abstract: An integrated circuit includes first to second transistors and a resistive device. The first transistor is coupled between a pad and a first voltage terminal that provides a first supply voltage. The second transistor is coupled in parallel with the first transistor. A breakdown voltage of the first transistor is different from a trigger voltage of the second transistor. The resistive device is coupled between the pad and a second voltage terminal that provides a second supply voltage higher than the first supply voltage, and operates with the second supply voltage in an electrostatic discharge (ESD) event when the first and second transistors discharge a ESD current between the pad and the first voltage terminal.
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公开(公告)号：US20250058128A1
公开(公告)日：2025-02-20
申请号：US18935150
申请日：2024-11-01
Inventor： Zheng-Long CHEN
Abstract: A semiconductor device includes substrate, a first gate structure, a second gate structure, and an epitaxy layer. The first gate structure and the second gate structure are over the substrate, in which the first gate structure and the second gate structure each comprises a shielding electrode, a gate electrode over the shielding electrode, and a first gate dielectric layer vertically separating the shielding electrode from the gate electrode. The epitaxy layer is over the substrate and cups an underside of the first gate structure and the second gate structure, in which the epitaxy layer comprises a doped region laterally between the first gate dielectric layer of the first gate structure and the first gate dielectric layer of the second gate structure, a dopant concentration of the doped region being non-uniform along a lateral direction.
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公开(公告)号：US20250057552A1
公开(公告)日：2025-02-20
申请号：US18937492
申请日：2024-11-05
Inventor： Zheng Long CHEN
Abstract: An integrated circuit includes a drain in a substrate, wherein the drain comprising a doped drain well. The doped drain well includes a first zone, wherein the first zone has a first concentration of a first dopant; and a second zone, wherein the second zone has a second concentration of the first dopant, a top-most surface of the first zone is coplanar with a top-most surface of the second zone, and the first concentration is different from the second concentration. The integrated circuit further includes a gate electrode over the substrate, the gate electrode being separated from each of the first zone and the second zone in a direction parallel to a top surface of the substrate by a distance greater than 0.
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公开(公告)号：US12211586B2
公开(公告)日：2025-01-28
申请号：US18476030
申请日：2023-09-27
Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD. , TSMC NANJING COMPANY LIMITED , TSMC CHINA COMPANY LIMITED
Inventor： Xiu-Li Yang , He-Zhou Wan , Mu-Yang Ye , Lu-Ping Kong , Ming-Hung Chang
Abstract: A device includes a first memory subarray, a first modulation circuit, a second memory subarray, a second modulation circuit and a control signal generator. The first modulation circuit is coupled to the first memory subarray. The second memory subarray is located between the first memory subarray and the first modulation circuit along a direction. The second modulation circuit is coupled to the second memory subarray. The control signal generator is configured to generate a first control signal to trigger the first modulation circuit according to a first length of the first memory subarray along the direction, and configured to generate a second control signal to trigger the second modulation circuit according to a second length of the second memory subarray along the direction.
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公开(公告)号：US12206038B2
公开(公告)日：2025-01-21
申请号：US17827571
申请日：2022-05-27
Inventor： Lianjie Li , Feng Han , Lu Zhang , Shengtian Lu , LinChun Gui , Chenglin Zhang
IPC: H01L31/105 , G01T1/24 , H01L27/146 , H01L31/0304
Abstract: A PIN diode detector includes a substrate. The PIN diode detector further includes a plurality of PIN diode wells in a pixel region, wherein each of the plurality of PIN diode wells has a first dopant type. The PIN diode detector further includes a connecting ring well and a plurality of floating ring wells in a peripheral region, wherein the connecting ring well and plurality of floating ring wells have the first dopant type. The PIN diode detector further includes a field stop ring well surrounding the plurality of floating ring wells, wherein the field stop ring well has a second dopant type opposite the first dopant type. The PIN diode detector further includes a blanket doped region. The blanket doped region extends continuously through an entirety of the pixel region and an entirety of the peripheral region, and the blanket doped region has the second dopant type.
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Patent Agency Ranking
公开(公告)号：US12176062B2
公开(公告)日：2024-12-24
申请号：US18336428
申请日：2023-06-16
Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD. , TSMC Nanjing Company Limited , TSMC China Company Limited
Inventor： He-Zhou Wan , Xiu-Li Yang , Pei-Le Li , Ching-Wei Wu
Abstract: A memory device includes a memory array, a first latch and a first logic element. The memory array is configured to operate according to a first global write signal. The first latch is configured to generate a first latch write data based on a clock signal. The first logic element is configured to generate the first global write signal based on the clock signal and the first latch write data.
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公开(公告)号：US20240387508A1
公开(公告)日：2024-11-21
申请号：US18785893
申请日：2024-07-26
Inventor： Kai ZHOU , Yaqi MA , Wei LI , Yongliang JIN , CunCun CHEN
IPC: H01L27/02 , G06F30/392 , H01L21/8238 , H01L23/528 , H01L27/092
Abstract: A method includes receiving a first power voltage at a gate and first terminal of a first transistor having a second terminal connected to a first node, the first power being gated to provide voltage in a first or a second state; receiving a voltage at a gate of a second transistor coupled between the first node and a ground node; receiving a second power voltage at a follower circuit coupled to the first node; turning on the second transistor to pull the first node toward ground, when the first power voltage is in the first state; turning off the second transistor when the first power voltage is in the second state; and discharging parasitic noise voltage of the first node through the first transistor during at least part of a period in which the first power voltage is in the second state and less than the second power voltage.
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公开(公告)号：US12148827B2
公开(公告)日：2024-11-19
申请号：US17884872
申请日：2022-08-10
Inventor： Zheng Long Chen
Abstract: A method of making an integrated circuit includes forming a drift region in a substrate, the drift region having a first dopant type; forming a drain well in the drift region, the drain well having the first dopant type. The drain well includes a first zone with a first concentration of the first dopant and a second zone having a second concentration of the first dopant different from the first concentration of the first dopant. The method further includes forming a source well in the substrate, the source well having a second dopant type opposite from the first dopant type, the source well being adjacent to the drift region in the substrate. The method includes forming a gate electrode over a top surface of the substrate over the drift region and the source well, and being laterally separated from the drain well. The method includes forming a drain low-density doped (LDD) region in the second zone of the drain well.
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公开(公告)号：US20240241495A1
公开(公告)日：2024-07-18
申请号：US18188260
申请日：2023-03-22
IPC: G05B19/18
CPC classification number: G05B19/188 , G05B2219/45031
Abstract: A method includes using a first pump apparatus to control a pressure condition of a first chamber, wherein the first pump apparatus produces a first operation data in a first digital protocol format; using a second pump apparatus to control a pressure condition of a second chamber, wherein the second pump apparatus produces a second operation data in a second digital protocol format different from the first digital protocol format; receiving, by a box device, the first operation data in the first digital protocol format and the second operation data in the second digital protocol format; decoding, by the box device, the first operation data in the first digital protocol format and the second operation data in the second digital protocol format; determining whether the first operation data is in an acceptable range; and adjusting the first pump apparatus to set the first operation data within the acceptable range.
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公开(公告)号：US11973083B2
公开(公告)日：2024-04-30
申请号：US17741410
申请日：2022-05-10
Inventor： Jian Wu , Feng Han , Shuai Zhang
IPC: H01L27/12 , H01L21/74 , H01L21/84 , H01L23/535
CPC classification number: H01L27/1203 , H01L21/743 , H01L21/84 , H01L23/535 , H01L27/1207
Abstract: A method of making an integrated circuit includes surrounding a first bias pad with dielectric material of a buried oxide layer. The method includes adding dopants to a layer of semiconductor material over the first bias pad. The method includes depositing a gate dielectric and a gate electrode over a top surface of the layer of semiconductor material. The method includes etching the gate dielectric and the gate electrode to isolate a gate electrode over the layer of semiconductor material. The method includes depositing an inter layer dielectric (ILD) material over the gate electrode and the layer of semiconductor material. The method includes etching at least one bias contact opening down to the first bias pad. The method includes filling the at least one bias contact opening with a bias contact material. The method includes electrically connecting at least one bias contact to an interconnect structure of the semiconductor device.
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