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    Power and signal line bussing method for memory devices
    1.
    发明授权
    Power and signal line bussing method for memory devices 失效
    用于存储器件的电源和信号线总线方法

    公开(公告)号：US5007025A

    公开(公告)日：1991-04-09

    申请号：US330917

    申请日：1989-03-31

    申请人： Sang K. Hwang ,  Tae S. Jung ,  Kyu H. Choi

    发明人： Sang K. Hwang ,  Tae S. Jung ,  Kyu H. Choi

    IPC分类号： G11C11/41 ,  G11C5/02 ,  G11C5/14 ,  G11C11/34 ,  G11C11/401 ,  H01L21/822 ,  H01L27/04 ,  H01L27/10

    CPC分类号： G11C5/025 ,  G11C5/14

    摘要： A memory cell device having circuitry located between memory cell arrays comprises power and ground lines to the circuitry formed directly above the memory cell arrays. The power and ground lines are parallel and positioned in an adjacent alternating pattern such that a power line is positioned adjacent a ground line, which is positioned adjacent another power line and so on. Signal lines carrying signals to and from the circuitry are also formed directly above memory cell arrays.

    摘要翻译： 具有位于存储单元阵列之间的电路的存储单元器件包括到存储单元阵列正上方形成的电路的电源和地线。 电源线和接地线平行并且位于相邻的交替图案中，使得电力线位于邻近另一电力线等的接地线附近。 在电路上传送信号的信号线也直接形成在存储单元阵列上方。

    Precharge circuit for use in a semiconductor memory device
    2.
    发明授权
    Precharge circuit for use in a semiconductor memory device 失效
    用于半导体存储器件的预充电电路

    公开(公告)号：US4852064A

    公开(公告)日：1989-07-25

    申请号：US207518

    申请日：1988-06-16

    申请人： Byung Y. Kim ,  Tae S. Jung ,  Sang K. Hwang

    发明人： Byung Y. Kim ,  Tae S. Jung ,  Sang K. Hwang

    IPC分类号： G11C11/41 ,  G11C11/40 ,  G11C11/419

    CPC分类号： G11C11/419

    摘要： A precharge circuit for use in a static random access memory is disclosed two step bit line pair precharging scheme in a precharge cycle performed prior to a read operation. The first precharging step is performed via each drain-source path of N-channel MOS transistor pair to the corresponding bit lines in response to a first pulse generated by the write enable signal and the following second precharging step is performed via means for precharging more dominantly than the transistor pair in response to a second pulse generated by the address transition detection circuit. Owing to the off-state of the N-channel MOS transistor pair in a read operation after a write operation, high speed read operation is obtained.

    摘要翻译： 在静态随机存取存储器中使用的预充电电路在读操作之前的预充电循环中公开了两步位线对预充电方案。 响应于由写入使能信号产生的第一脉冲，第一预充电步骤经由N沟道MOS晶体管对的每个漏极 - 源极路径执行到对应的位线，并且随后的第二预充电步骤经由用于更主要地预充电的装置 响应于由地址转换检测电路产生的第二脉冲的晶体管对。 由于在写入操作之后的读取操作中N沟道MOS晶体管对的截止状态，因此获得高速读取操作。