公开(公告)号：US20060262230A1

公开(公告)日：2006-11-23

申请号：US11431324

申请日：2006-05-10

申请人： Manabu Ookubo ,  Akio Yokoyama ,  Masayuki Ozasa ,  Takao Soramoto

发明人： Manabu Ookubo ,  Akio Yokoyama ,  Masayuki Ozasa ,  Takao Soramoto

IPC分类号： H04N5/50

CPC分类号： H04B1/28 ,  H04N5/4446

摘要： The receiver IF system or the signal selection device of the present invention includes: frequency converters that obtain polyphase intermediate-frequency signals for suppressing an image component of an RF signal from an input signal; a polyphase filter for removing an image component from the polyphase intermediate-frequency signals; and a band-pass filter composed of an N-pass filter for selecting a channel of an intermediate-frequency signal that is obtained by removing an image component from an output of the polyphase filter. An image rejection filter and a channel selection filter can be integrated at low cost with higher performance, and an area of a substrate for reception can be reduced.

摘要翻译： 本发明的接收机IF系统或信号选择装置包括：频率转换器，其从输入信号获得用于抑制RF信号的图像分量的多相中频信号; 用于从所述多相中频信号中去除图像分量的多相滤波器; 以及带通滤波器，其由用于选择通过从多相滤波器的输出去除图像分量而获得的中频信号的通道的N通滤波器组成。 可以以低成本，高性能地集成图像抑制滤波器和通道选择滤波器，并且可以减少用于接收的基板的面积。

公开(公告)号：US08482275B2

公开(公告)日：2013-07-09

申请号：US12840738

申请日：2010-07-21

申请人： Takao Soramoto ,  Hitoshi Kobayashi

发明人： Takao Soramoto ,  Hitoshi Kobayashi

IPC分类号： G01R25/00

CPC分类号： G01P15/125 ,  G01C19/56 ,  G01C19/5607 ,  G01D3/028

摘要： A PLL circuit generates a plurality of oscillated clocks having different phases. A selector selects one of the plurality of oscillated clocks generated by the PLL circuit. A detection circuit detects a physical quantity signal corresponding to the physical quantity given to a physical quantity sensor from a sensor signal received from the physical quantity sensor based on the oscillated clock selected by the selector.

摘要翻译： PLL电路产生具有不同相位的多个振荡时钟。 选择器选择由PLL电路产生的多个振荡时钟之一。 检测电路根据由选择器选择的振荡时钟，从物理量传感器接收到的传感器信号，检测与物理量传感器对应的物理量对应的物理量信号。

公开(公告)号：US07405636B2

公开(公告)日：2008-07-29

申请号：US11409764

申请日：2006-04-24

申请人： Masayuki Ozasa ,  Akio Yokoyama ,  Manabu Ookubo ,  Takao Soramoto

发明人： Masayuki Ozasa ,  Akio Yokoyama ,  Manabu Ookubo ,  Takao Soramoto

IPC分类号： H03H7/06 ,  H01L21/822

CPC分类号： H03H7/21

摘要： Four input nodes I1-I4 for inputting 4-phase signals, four resistors R1-R4, four capacitors C1-C4, and four output nodes O1-O4 for outputting 4-phase signals are provided. The resistors and the capacitors are connected alternately in a loop, and the input nodes and output nodes are connected alternately to the respective nodes between the resistors and the capacitors sequentially. Each of the four resistors is composed of a group of three or more partial resistors, and three groups of the partial resistors R2a-R2c, R3a-R3c and R4a-R4c are collected respectively and arranged in the same attitude, while the partial resistors R1a-R1c of the remaining group are distributed into the other groups and arranged in the same line the same attitude as the partial resistors of each of the other groups. The regions of the thus collected groups are arranged in one direction. By simplifying the layout of the components and the shape of the wirings, influences on the characteristics by the parasitic elements are reduced, and complication in the layout and wirings can be suppressed even when using plural stages.

摘要翻译： 提供用于输入四相信号的四个输入节点I 1 -I 4，四个电阻器R 1 -R 4，四个电容器C 1 -C 4和用于输出4相信号的四个输出节点O 1〜4 4。 电阻器和电容器以环路交替连接，并且输入节点和输出节点交替地连接到电阻器和电容器之间的相应节点。 四个电阻器中的每一个由三​​个或更多个部分电阻器组成，并且三个部分电阻器R 2 aR 2 c，R 3 aR 3 c和R 4 aR 4 c分别被收集并且以相同的姿态 ，而剩余组的部分电阻器R 1 aR 1 c分配到其他组中，并且以与每个其他组的部分电阻器相同的姿态排列成同一行。 这样收集的组的区域被布置在一个方向上。 通过简化部件的布局和配线的形状，减少了寄生元件对特性的影响，并且即使在使用多级时也能够抑制配线和布线的复杂化。

公开(公告)号：US20070129041A1

公开(公告)日：2007-06-07

申请号：US11605320

申请日：2006-11-29

申请人： Akio Yokoyama ,  Manabu Ookubo ,  Masayuki Ozasa ,  Takao Soramoto

发明人： Akio Yokoyama ,  Manabu Ookubo ,  Masayuki Ozasa ,  Takao Soramoto

IPC分类号： H04B1/18

CPC分类号： H04B1/28

摘要： An intermediate-frequency signal from a frequency mixer is subjected to channel selection by a band-pass filter. Then an output signal from the band-pass filter is subjected to analog-to-digital conversion by an analog-to-digital converter on a predetermined sampling frequency. An anti-aliasing filter is provided at a stage previous to the analog-to-digital converter. The anti-aliasing filter includes notch filters and attenuates signals with frequencies which are higher and lower than a frequency which is an integral multiple of the sampling frequency by the intermediate frequency.

摘要翻译： 来自混频器的中频信号通过带通滤波器进行信道选择。 然后，来自带通滤波器的输出信号在模拟数字转换器上以预定的采样频率进行模数转换。 在模数转换器之前的阶段提供抗混叠滤波器。 抗混叠滤波器包括陷波滤波器，并衰减频率高于和低于采样频率乘以中频的整数倍的频率的信号。

公开(公告)号：US20100289480A1

公开(公告)日：2010-11-18

申请号：US12840738

申请日：2010-07-21

申请人： Takao Soramoto ,  Hitoshi Kobayashi

发明人： Takao Soramoto ,  Hitoshi Kobayashi

IPC分类号： G01R25/00

CPC分类号： G01P15/125 ,  G01C19/56 ,  G01C19/5607 ,  G01D3/028

摘要： A PLL circuit generates a plurality of oscillated clocks having different phases. A selector selects one of the plurality of oscillated clocks generated by the PLL circuit. A detection circuit detects a physical quantity signal corresponding to the physical quantity given to a physical quantity sensor from a sensor signal received from the physical quantity sensor based on the oscillated clock selected by the selector.

摘要翻译： PLL电路产生具有不同相位的多个振荡时钟。 选择器选择由PLL电路产生的多个振荡时钟之一。 检测电路根据由选择器选择的振荡时钟，从物理量传感器接收到的传感器信号，检测与物理量传感器对应的物理量对应的物理量信号。

公开(公告)号：US20060244551A1

公开(公告)日：2006-11-02

申请号：US11409764

申请日：2006-04-24

申请人： Masayuki Ozasa ,  Akio Yokoyama ,  Manabu Ookubo ,  Takao Soramoto

发明人： Masayuki Ozasa ,  Akio Yokoyama ,  Manabu Ookubo ,  Takao Soramoto

IPC分类号： H03H7/01

CPC分类号： H03H7/21

摘要： Four input nodes I1-I4 for inputting 4-phase signals, four resistors R1-R4, four capacitors C1-C4, and four output nodes O1-O4 for outputting 4-phase signals are provided. The resistors and the capacitors are connected alternately in a loop, and the input nodes and output nodes are connected alternately to the respective nodes between the resistors and the capacitors sequentially. Each of the four resistors is composed of a group of three or more partial resistors, and three groups of the partial resistors R2a-R2c, R3a-R3c and R4a-R4c are collected respectively and arranged in the same attitude, while the partial resistors R1a-R1c of the remaining group are distributed into the other groups and arranged in the same line the same attitude as the partial resistors of each of the other groups. The regions of the thus collected groups are arranged in one direction. By simplifying the layout of the components and the shape of the wirings, influences on the characteristics by the parasitic elements are reduced, and complication in the layout and wirings can be suppressed even when using plural stages.

摘要翻译： 提供用于输入四相信号的四个输入节点I 1 -I 4，四个电阻器R 1 -R 4，四个电容器C 1 -C 4和用于输出4相信号的四个输出节点O 1〜4 4。 电阻器和电容器以环路交替连接，并且输入节点和输出节点交替地连接到电阻器和电容器之间的相应节点。 四个电阻器中的每一个由三​​个或更多个部分电阻器组成，并且三个部分电阻器R 2 aR 2 c，R 3 aR 3 c和R 4 aR 4 c分别被收集并且以相同的姿态 ，而剩余组的部分电阻器R 1 aR 1 c分配到其他组中，并且以与每个其他组的部分电阻器相同的姿态排列成同一行。 这样收集的组的区域被布置在一个方向上。 通过简化部件的布局和配线的形状，减少了寄生元件对特性的影响，并且即使在使用多级时也能够抑制配线和布线的复杂化。