公开(公告)号：US08482275B2

公开(公告)日：2013-07-09

申请号：US12840738

申请日：2010-07-21

申请人： Takao Soramoto ,  Hitoshi Kobayashi

发明人： Takao Soramoto ,  Hitoshi Kobayashi

IPC分类号： G01R25/00

CPC分类号： G01P15/125 ,  G01C19/56 ,  G01C19/5607 ,  G01D3/028

摘要： A PLL circuit generates a plurality of oscillated clocks having different phases. A selector selects one of the plurality of oscillated clocks generated by the PLL circuit. A detection circuit detects a physical quantity signal corresponding to the physical quantity given to a physical quantity sensor from a sensor signal received from the physical quantity sensor based on the oscillated clock selected by the selector.

摘要翻译： PLL电路产生具有不同相位的多个振荡时钟。 选择器选择由PLL电路产生的多个振荡时钟之一。 检测电路根据由选择器选择的振荡时钟，从物理量传感器接收到的传感器信号，检测与物理量传感器对应的物理量对应的物理量信号。

公开(公告)号：US20100289480A1

公开(公告)日：2010-11-18

申请号：US12840738

申请日：2010-07-21

申请人： Takao Soramoto ,  Hitoshi Kobayashi

发明人： Takao Soramoto ,  Hitoshi Kobayashi

IPC分类号： G01R25/00

CPC分类号： G01P15/125 ,  G01C19/56 ,  G01C19/5607 ,  G01D3/028

摘要： A PLL circuit generates a plurality of oscillated clocks having different phases. A selector selects one of the plurality of oscillated clocks generated by the PLL circuit. A detection circuit detects a physical quantity signal corresponding to the physical quantity given to a physical quantity sensor from a sensor signal received from the physical quantity sensor based on the oscillated clock selected by the selector.

摘要翻译： PLL电路产生具有不同相位的多个振荡时钟。 选择器选择由PLL电路产生的多个振荡时钟之一。 检测电路根据由选择器选择的振荡时钟，从物理量传感器接收到的传感器信号，检测与物理量传感器对应的物理量对应的物理量信号。

公开(公告)号：US20180151877A2

公开(公告)日：2018-05-31

申请号：US15526707

申请日：2015-11-12

申请人： Shinichi Maruyama ,  Koji Nitta ,  Shoichiro Sakai ,  Atsushi Fukunaga ,  Eiko Imazaki ,  Koma Numata ,  Hideaki Ito ,  Hitoshi Kobayashi ,  Toshiaki Yamashita ,  Shinichi Maruyama

发明人： Koji Nitta ,  Shoichiro Sakai ,  Atsushi Fukunaga ,  Eiko Imazaki ,  Koma Numata ,  Hideaki Ito ,  Hitoshi Kobayashi ,  Toshiaki Yamashita

IPC分类号： H01M4/38 ,  H01M10/0564

CPC分类号： H01M4/381 ,  H01G11/04 ,  H01G11/30 ,  H01G11/62 ,  H01G11/86 ,  H01M4/0459 ,  H01M4/134 ,  H01M4/1395 ,  H01M4/362 ,  H01M10/054 ,  H01M10/0564 ,  H01M10/0566 ,  Y02E60/13

摘要： Provided is a method for producing a negative electrode for an electric storage device, the method comprising the steps of: preparing a negative electrode composition comprising a negative electrode active material that reversibly carries a sodium ion, metal sodium, and a liquid dispersion medium for dispersing them; allowing a negative electrode current collector to hold the negative electrode composition; evaporating at least part of the liquid dispersion medium from the negative electrode composition held by the negative electrode current collector, thereby giving a negative electrode precursor comprising the negative electrode active material, the metal sodium, and the negative electrode current collector; and bringing the negative electrode precursor into contact with an electrolyte having sodium ion conductivity, thereby doping the negative electrode active material with sodium eluted from the metal sodium.

公开(公告)号：US08486291B2

公开(公告)日：2013-07-16

申请号：US13011070

申请日：2011-01-21

申请人： Takeshi Ohmori ,  Yasuhiro Nishimori ,  Hiroaki Ishimura ,  Hitoshi Kobayashi ,  Masamichi Sakaguchi

发明人： Takeshi Ohmori ,  Yasuhiro Nishimori ,  Hiroaki Ishimura ,  Hitoshi Kobayashi ,  Masamichi Sakaguchi

IPC分类号： C03C15/00

CPC分类号： H01J37/32816 ,  B08B7/0035 ,  H01J37/32834

摘要： In the present invention, provided is a plasma processing method which reduces or eliminates the emission of contaminating matters caused by a quality-altered layer on the surface of yttria of a processing chamber's inner wall and parts inside the processing chamber. It is the plasma processing method including an etching step of setting a sample inside the processing chamber, and etching the sample, a deposition-product removing step of removing a deposition product by using a plasma, the deposition product being deposited inside the processing chamber by the etching step, the plasma being generated using a gas which contains fluorine or chlorine, and a step of exposing, to a rare-gas-based plasma, the inside of the processing chamber after the deposition-product removing step.

摘要翻译： 在本发明中，提供了一种等离子体处理方法，其减少或消除由处理室的内壁和处理室内的部件的氧化钇的表面上的质量变化层引起的污染物质的排放。 等离子体处理方法包括在处理室内设置样品并蚀刻样品的蚀刻步骤，通过使用等离子体去除沉积产物的沉积产物去除步骤，沉积产物通过 蚀刻步骤，使用含有氟或氯的气体产生等离子体，以及在沉积物除去步骤之后将稀释气体等离子体暴露于处理室内部的步骤。

公开(公告)号：US20110242091A1

公开(公告)日：2011-10-06

申请号：US12879937

申请日：2010-09-10

申请人： Hitoshi Kobayashi ,  Tatsuo Saishu ,  Yoshiyuki Kokojima

发明人： Hitoshi Kobayashi ,  Tatsuo Saishu ,  Yoshiyuki Kokojima

IPC分类号： G06T15/00

CPC分类号： G09G5/399 ,  G06T1/60 ,  G09G3/003 ,  H04N13/161 ,  H04N13/31

摘要： An image processing circuit includes a first memory, a second memory, a write unit and a read unit. The first and second memories alternately store sub pixels of an input image including a plurality of parallax images corresponding to different view point directions. The write unit writes the sub pixels to one of the first and second memories. The read unit reads the sub pixels as an output image from the other of the first and second memories. Each of the first and second memories stores sub pixels for a plurality of successive lines. While the write unit writes the sub pixels of the input image to one of the first and second memories, the read unit reads the sub pixels of the output image from the other of the first and second memories. The first and the second memories are alternately changed.

摘要翻译： 图像处理电路包括第一存储器，第二存储器，写入单元和读取单元。 第一和第二存储器交替地存储包括对应于不同视点方向的多个视差图像的输入图像的子像素。 写单元将子像素写入第一和第二存储器之一。 读取单元从第一和第二存储器中的另一个读取作为输出图像的子像素。 第一和第二存储器中的每一个存储多个连续行的子像素。 当写入单元将输入图像的子像素写入第一和第二存储器之一时，读取单元从第一和第二存储器中的另一个读取输出图像的子像素。 第一和第二存储器交替地改变。

公开(公告)号：US07439893B2

公开(公告)日：2008-10-21

申请号：US11776748

申请日：2007-07-12

申请人： Fumihito Inukai ,  Hitoshi Kobayashi

发明人： Fumihito Inukai ,  Hitoshi Kobayashi

IPC分类号： H03M3/00

CPC分类号： H03M7/3022 ,  H03F3/2175 ,  H03M7/3042

摘要： By using a selector, an output of a delta sigma modulator having a quantizer for quantizing a signal is selectively supplied to one of a first D/A converter having a linear amplifier and a second D/A converter having a digital amplifier. Further, the number of quantization levels of the quantizer, the sampling frequency, or the order of a transfer function of the delta sigma modulator is selected by a control signal selector in conjunction with the selector. An output of the first D/A converter is supplied to a line terminal, while an output of the second D/A converter is supplied to a headphone terminal.

摘要翻译： 通过使用选择器，具有用于量化信号的量化器的Δ-Σ调制器的输出被选择性地提供给具有线性放大器的第一D / A转换器和具有数字放大器的第二D / A转换器之一。 此外，控制信号选择器与选择器一起选择量化器的量化级数，采样频率或ΔΣ调制器的传递函数的阶数。 第一D / A转换器的输出被提供给线路终端，而第二D / A转换器的输出被提供给耳机终端。

公开(公告)号：US07439605B2

公开(公告)日：2008-10-21

申请号：US11117331

申请日：2005-04-29

申请人： Hitoshi Kobayashi ,  Tomoki Inoue ,  Satoshi Aida ,  Yasushi Takahashi

发明人： Hitoshi Kobayashi ,  Tomoki Inoue ,  Satoshi Aida ,  Yasushi Takahashi

IPC分类号： H01L29/76

CPC分类号： H01L29/7802 ,  H01L21/26586 ,  H01L29/0634 ,  H01L29/0653 ,  H01L29/0696 ,  H01L29/405 ,  H01L29/408 ,  H01L29/66712 ,  H01L29/7801

摘要： A semiconductor device include a plurality of active element cells including first element regions of a first conductivity type and second element regions of a second conductivity type, the second element regions disposed between the first element regions; and isolation regions disposed between the active element cells so as to isolate the active element cells from each other, the isolation regions being filled with a plurality of semi-insulating particles including granular insulators covered by semiconductor films.

摘要翻译： 半导体器件包括多个有源元件单元，其包括第一导电类型的第一元件区域和第二导电类型的第二元件区域，第二元件区域设置在第一元件区域之间; 以及设置在有源元件单元之间以隔离有源元件元件的隔离区域，隔离区域填充有多个包含半导体膜覆盖的粒状绝缘体的半绝缘粒子。

公开(公告)号：US20080054718A1

公开(公告)日：2008-03-06

申请号：US11837177

申请日：2007-08-10

申请人： Kimio Nishino ,  Toshiharu Sugawara ,  Kenichiro Matsubara ,  Toshiyuki Innami ,  Hitoshi Kobayashi

发明人： Kimio Nishino ,  Toshiharu Sugawara ,  Kenichiro Matsubara ,  Toshiyuki Innami ,  Hitoshi Kobayashi

IPC分类号： B60T8/60 ,  G06F17/00

CPC分类号： B60T8/1755 ,  B60T8/3255 ,  B60T8/4072 ,  B60T8/885 ,  B60T17/22 ,  B60T17/221 ,  B60T2270/402

摘要： Even in the case that at least one braking force generating function fails, it is possible to secure a maximum braking force as well as suppressing a yaw moment generated on the basis of the failure as much as possible even at a time when whatever braking force is requested, A target braking force to a normal brake apparatus is calculated on the basis of a result of detection by a malfunction detecting portion, in such a manner that a total of braking forces generated in the brake apparatuses in respective wheels becomes as equal as possible to a requested braking force, at a time when a malfunction is generated in the brake apparatus or a braking force control portion.

摘要翻译： 即使在至少一个制动力产生功能失效的情况下，也可以确保最大的制动力，并且能够尽可能地抑制基于故障而产生的横摆力矩，即使在任何制动力为 根据故障检测部的检测结果，对各个车轮中的制动装置中产生的制动力的总和变得相等，来计算向正常制动装置的目标制动力 在制动装置或制动力控制部分中产生故障时，要求制动力。

公开(公告)号：US07319420B2

公开(公告)日：2008-01-15

申请号：US11338651

申请日：2006-01-25

申请人： Masato Nakakita ,  Fumihito Inukai ,  Hitoshi Kobayashi

发明人： Masato Nakakita ,  Fumihito Inukai ,  Hitoshi Kobayashi

IPC分类号： H03M3/00

CPC分类号： H03M3/394 ,  H03M3/414

摘要： A cascade-type variable-order delta-sigma modulator with low power consumption that can change the number of stages of the quantization loops, which are connected in a cascade configuration, to an optimum number depending on peripheral circuitries in a configuration as simple as possible. The present invention includes first to nth stages of delta-sigma modulating type quantization loops (n is an integer equal to or more than 2) connected in a cascade configuration, and a noise rejecting circuit. Each quantization loop quantizes an input signal, outputs the quantization result, and feeds back the quantization result to itself. The noise rejecting circuit rejects a quantization noise of the first stage of quantization loop, and comprises (n−1) selectors for activating and de-activating the respective output signals of the second and succeeding stages of the quantization loops in compliance with the control signal.

摘要翻译： 具有低功耗的级联型可变阶Δ-Σ调制器，其可以将串联配置中连接的量化循环的级数改变为最佳数量，这取决于尽可能简单的配置中的外设电路 。 本发明包括以级联配置连接的Δ-Σ调制型量化环（n为等于或大于2的整数）的第一至第N级，以及噪声抑制电路。 每个量化环对输入信号进行量化，输出量化结果，并将量化结果反馈给自身。 噪声抑制电路拒绝量化环路的第一级的量化噪声，并且包括用于根据控制信号激活和去激活量化环路的第二级和后级的各个输出信号的（n-1）个选择器 。

公开(公告)号：US20070166457A1

公开(公告)日：2007-07-19

申请号：US10548202

申请日：2004-03-08

申请人： Hisayoshi Yamoto ,  Kazuya Akuto ,  Ken Nagaoka ,  Hitoshi Kobayashi ,  Masafumi Shoji ,  Mitsuru Fukugawa

发明人： Hisayoshi Yamoto ,  Kazuya Akuto ,  Ken Nagaoka ,  Hitoshi Kobayashi ,  Masafumi Shoji ,  Mitsuru Fukugawa

IPC分类号： C23C16/00

CPC分类号： C23C16/448

摘要： It is aimed at providing a vaporization apparatus and a vaporization method capable of keeping track of a progressive condition of clogging of the apparatus. It is also aimed at providing a vaporization apparatus and a vaporization method capable of eliminating clogging prior to occurrence of complete clogging, without disassembling the apparatus. It provides a vaporization apparatus for introducing a carrier gas from one end of a gas passage and for feeding, the carrier gas including a material solution, from the other end of the gas passage to a vaporization part to thereby vaporize the material solution, characterized in that a mass flow controller (MFC) is provided at the one end of the gas passage, and means for detecting a pressure within the gas passage is provided. The vaporization apparatus is characterized in that the same is provided with means for introducing a chemical solution capable of dissolving therein matters deposited or sticked to the inside of the gas passage, into the gas passage.

摘要翻译： 其目的在于提供能够跟踪装置堵塞的进行状态的蒸发装置和蒸发方法。 还旨在提供一种能够在没有完全堵塞的情况下消除堵塞而不拆卸设备的蒸发装置和蒸发方法。 它提供了一种用于从气体通道的一端引入载气并用于将包括材料溶液的载气从气体通道的另一端引入蒸发部分从而汽化该材料溶液的蒸发装置，其特征在于， 在气体通道的一端设置质量流量控制器（MFC），并且提供用于检测气体通道内的压力的装置。 蒸发装置的特征在于，其具有用于将能够溶解在气体通道内部的物质中的化学溶液引入气体通道的装置。