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公开(公告)号：US06446159B1
公开(公告)日：2002-09-03
申请号：US09242049
申请日：1999-02-08
申请人： Koji Kai , Taku Ohsawa , Kazuaki Murakami
发明人： Koji Kai , Taku Ohsawa , Kazuaki Murakami
IPC分类号： G06F1200
摘要： An object of the invention, in a semiconductor circuit or, more particularly, in an LSI on which a DRAM and a logic circuit are merged, is to decrease the frequency of times of refreshing operations to thereby achieve both reduction in power consumption and prevention of deterioration in the performance of the logic circuit caused by an increase in the memory access time due to contention between refresh and DRAM access of the logic circuit. To achieve the object, the refreshing is done only for rows storing the data used by the logic portion. Further, arbitrary data for which periods from being written in to being read out are overlapping or close to each other are allocated to the same row of the DRAM so as to be stored thereon, and the row is refreshed only during the period of time that the data stored thereon is live.
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公开(公告)号：US07281250B2
公开(公告)日：2007-10-09
申请号：US10133409
申请日：2002-04-29
申请人： Taku Ohsawa , Satoshi Matsushita
发明人： Taku Ohsawa , Satoshi Matsushita
CPC分类号： G06F9/3851
摘要： With a single program divided into a plurality of threads A to C, at the execution of the threads in parallel to each other by a plurality of processors, determination is made of a forkability of a slave thread into other processor in response to a fork instruction in a master thread being executed by a predetermined processor and when forkable, the slave thread is forked into other processor and when not forkable, the fork instruction is invalidated to execute an instruction subsequent to the fork instruction by the predetermined processor and then execute a group of instructions of the slave thread by the predetermined processor.
摘要翻译： 通过分割成多个线程A到C的单个程序，在由多个处理器彼此并行执行线程时，响应于叉指令确定从线程到其他处理器的可分割性 在由预定处理器执行的主线程中，并且当叉形时，从线程被分叉到其他处理器中，并且当不可分叉时，叉指令无效以执行预定处理器之后的叉指令之后的指令，然后执行组 的预定处理器的从线程的指令。
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公开(公告)号：US07082601B2
公开(公告)日：2006-07-25
申请号：US10196613
申请日：2002-07-17
IPC分类号： G06F9/45
CPC分类号： G06F9/4806 , G06F9/3842 , G06F9/3851
摘要： In a parallel processor system for executing a plurality of threads in parallel to each other by a plurality of thread execution units, the respective thread execution units allow for forking of a slave thread from an individual thread execution unit into another arbitrary thread execution unit. The respective thread execution units are managed in three states, a free state where fork is possible, a busy state where a thread is being executed, and a term state where a thread being terminated and yet to be settled exists. At the time of forking of a new thread, when there exists no thread execution unit at the free state, a thread that the thread execution unit at the term state has is merged into its immediately succeeding slave thread to bring the thread execution unit in question to the free state and conduct forking of a new thread.
摘要翻译： 在用于通过多个线程执行单元彼此并行地执行多个线程的并行处理器系统中，各个线程执行单元允许将从线程从单独的线程执行单元分支到另一个任意线程执行单元。 相应的线程执行单元以三种状态进行管理，其中fork是可用的空闲状态，正在执行线程的忙状态以及线程被终止且尚待结算的项状态。 在分配新线程时，如果在空闲状态下不存在线程执行单元，那么术语状态下的线程执行单元的线程被合并到其紧随的从线程中，从而使线程执行单元出现问题 到自由状态，并进行划线新线程。
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公开(公告)号：US06907517B2
公开(公告)日：2005-06-14
申请号：US10163505
申请日：2002-06-07
申请人： Taku Ohsawa , Satoshi Matsushita
发明人： Taku Ohsawa , Satoshi Matsushita
CPC分类号： G06F9/3828 , G06F9/3009 , G06F9/3824 , G06F9/3838 , G06F9/3842 , G06F9/3851
摘要： In a parallel processor system for executing a plurality of threads which are obtained by dividing a single program in parallel each other by a plurality of processors, when a processor executing a master thread conducts forking of a slave thread in other processor, at every write to a general register in the master thread after forking, the fork source processor transmits an updated register value to the fork destination processor through a communication bus. The fork destination processor executes the slave thread for speculation and upon detecting an offense against Read After Write (RAW) related to the general register, cancels the thread being executed to conduct re-execution of the thread.
摘要翻译： 在用于执行通过多个处理器并行地分割单个程序而获得的多个线程的并行处理器系统中，当执行主线程的处理器在其他处理器中执行从线程的分支时，每次写入 在分叉后的主线程中的通用寄存器，叉源处理器通过通信总线向fork目的地处理器发送更新的寄存器值。 叉目的处理器执行从线程以进行推测，并且在检测到与通用寄存器相关的写入后读取（RAW）的进攻时，取消正在执行的线程以重新执行线程。
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公开(公告)号：US07243345B2
公开(公告)日：2007-07-10
申请号：US10189455
申请日：2002-07-08
申请人： Taku Ohsawa , Satoshi Matsushita
发明人： Taku Ohsawa , Satoshi Matsushita
CPC分类号： G06F9/4806 , G06F9/3009 , G06F9/3851
摘要： In a multi-thread executing method of dividing a single program into a plurality of threads and executing the program by a plurality of processors in parallel, at a time of every fork instruction of the executing thread, when there already exists a child thread generated form the above thread, the program cancels the child thread or makes invalid all the fork instructions other than the first fork instruction having succeeded in forking the child thread, hence to select one fork instruction for creating an effective child thread from a plurality of fork instructions existing within a parent thread, during the execution of the parent thread. Therefore, it can assure the Fork-Once limitation at a time of the program execution.
摘要翻译： 在将单个程序划分为多个线程并且由并行执行多个处理器执行程序的多线程执行方法中，在执行线程的每个fork指令时，当存在子线程生成形式时 在上述线程中，程序取消子线程，或使得第一叉指令之外的所有叉指令成功地无效，从而从存在的多个叉指令中选择用于创建有效子线程的一个叉指令 在父线程中，在执行父线程期间。 因此，可以在程序执行时确保“叉一次”限制。
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公开(公告)号：US07134124B2
公开(公告)日：2006-11-07
申请号：US10174953
申请日：2002-06-20
申请人： Taku Ohsawa , Satoshi Matsushita
发明人： Taku Ohsawa , Satoshi Matsushita
CPC分类号： G06F9/4806
摘要： Each processor comprises a register for storing start address of a forked child thread and a comparator for detecting that the value of its own program counter is coincident with the start address stored in this register. Each processor sends a thread stop notice to a thread controller when the value of its own program counter is coincident with the start address of the forked child thread and ends the execution of a parent thread when receiving a thread end permission from the thread controller.
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