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公开(公告)号：US07082601B2
公开(公告)日：2006-07-25
申请号：US10196613
申请日：2002-07-17
IPC分类号： G06F9/45
CPC分类号： G06F9/4806 , G06F9/3842 , G06F9/3851
摘要： In a parallel processor system for executing a plurality of threads in parallel to each other by a plurality of thread execution units, the respective thread execution units allow for forking of a slave thread from an individual thread execution unit into another arbitrary thread execution unit. The respective thread execution units are managed in three states, a free state where fork is possible, a busy state where a thread is being executed, and a term state where a thread being terminated and yet to be settled exists. At the time of forking of a new thread, when there exists no thread execution unit at the free state, a thread that the thread execution unit at the term state has is merged into its immediately succeeding slave thread to bring the thread execution unit in question to the free state and conduct forking of a new thread.
摘要翻译： 在用于通过多个线程执行单元彼此并行地执行多个线程的并行处理器系统中，各个线程执行单元允许将从线程从单独的线程执行单元分支到另一个任意线程执行单元。 相应的线程执行单元以三种状态进行管理，其中fork是可用的空闲状态，正在执行线程的忙状态以及线程被终止且尚待结算的项状态。 在分配新线程时，如果在空闲状态下不存在线程执行单元，那么术语状态下的线程执行单元的线程被合并到其紧随的从线程中，从而使线程执行单元出现问题 到自由状态，并进行划线新线程。
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公开(公告)号：US06950908B2
公开(公告)日：2005-09-27
申请号：US10191401
申请日：2002-07-10
CPC分类号： G06F12/0815
摘要： The processors #0 to #3 execute a plurality of threads whose execution sequence is defined, in parallel. When the processor #1 that executes a thread updates the self-cache memory #1, if the data of the same address exists in the cache memory #2 of the processor #2 that executes a child thread, it updates the cache memory #2 simultaneously, but even if it exists in the cache memory #0 of the processor #0 that executes a parent thread, it doesn't rewrite the cache memory #0 but only records that rewriting has been performed in the cache memory #1. When the processor #0 completes a thread, a cache line with the effect that the data has been rewritten recorded from a child thread may be invalid and a cache line without such record is judged to be effective. Whether a cache line which may be invalid is really invalid or effective is examined during execution of the next thread.
摘要翻译： 处理器＃0到＃3并行地执行执行顺序的多个线程。 当执行线程的处理器＃1更新自缓存存储器＃1时，如果在执行子线程的处理器＃2的高速缓存存储器＃2中存在相同地址的数据，则其更新高速缓存存储器＃2 同时，即使存在执行母线程的处理器＃0的高速缓存存储器＃0中，也不会重写高速缓存存储器＃0，而仅记录在高速缓冲存储器＃1中进行了重写。当 处理器＃0完成线程，具有从子线程重写的数据的高速缓存行可能是无效的，并且没有这样的记录的高速缓存行被判断为有效。 在执行下一个线程期间是否检查可能无效的高速缓存行真正无效或有效。
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3.发明授权PROCESSOR, MULTIPROCESSOR SYSTEM AND METHOD FOR SPECULATIVELY EXECUTING MEMORY OPERATIONS USING MEMORY TARGET ADDRESSES OF THE MEMORY OPERATIONS TO INDEX INTO A SPECULATIVE EXECUTION RESULT HISTORY STORAGE MEANS TO PREDICT THE OUTCOME OF THE MEMORY OPERATION 失效处理器，多处理器系统和使用存储器操作的存储器目标地址进行规范执行结果的存储器操作的方法用于预测存储器操作的结果的历史存储公开(公告)号：US06970997B2
公开(公告)日：2005-11-29
申请号：US10151819
申请日：2002-05-22
CPC分类号： G06F9/383 , G06F9/3832 , G06F9/3834 , G06F9/3838 , G06F9/3842
摘要： When a processor executes a memory operation instruction by means of data dependence speculative execution, a speculative execution result history table which stores history information concerning success/failure results of the speculative execution of memory operation instructions of the past is referred to and thereby whether the speculative execution will succeed or fail is predicted. In the prediction, the target address of the memory operation instruction is converted by a hash function circuit into an entry number of the speculative execution result history table (allowing the existence of aliases), and an entry of the table designated by the entry number is referred to. If the prediction is “success”, the memory operation instruction is executed in out-of-order execution speculatively (with regard to data dependence relationship between the instructions). If the prediction is “failure”, the speculative execution is canceled and the memory operation instruction is executed later in the program order non-speculatively. Whether the speculative execution of the memory operation instructions has succeeded or failed is judged by detecting the data dependence relationship between the memory operation instructions, and the speculative execution result history table is updated taking the judgment into account.
摘要翻译： 当处理器通过数据依赖性推测执行执行存储器操作指令时，参考存储关于过去的存储器操作指令的推测执行的成功/失败结果的历史信息的推测执行结果历史表，从而参考 预测执行成功或失败。 在预测中，存储器操作指令的目标地址由散列函数电路转换为推测执行结果历史表的条目号（允许存在别名），并且由条目号指定的表的条目是 参考。 如果预测为“成功”，则存储器操作指令以推定性的无序执行（关于指令之间的数据依赖关系）执行。 如果预测为“故障”，则推测性执行被取消，并且以非推测方式在程序顺序中稍后执行存储器操作指令。 通过检测存储器操作指令之间的数据依赖关系来判断存储器操作指令的推测执行是成功还是失败，并且考虑到判断来更新推测执行结果历史表。
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4.发明申请Data dependency detection using history table of entry number hashed from memory address 有权使用从存储器地址散列的入口号历史表的数据相关性检测公开(公告)号：US20050216705A1
公开(公告)日：2005-09-29
申请号：US11126310
申请日：2005-05-11
CPC分类号： G06F9/3834 , G06F9/3838 , G06F9/3842
摘要： A detector detects at least one kind of dependence in address between instructions executed by at least a processor, the detector being adopted to detect a possibility of presence of the at least one kind of dependence, wherein if the at least one kind of dependence is present in fact, then the detector detects a possibility of presence of the at least one kind of dependence, and if the at least one kind of dependence is not present in fact, then the detector may detect a pseudo presence of the at least one kind of dependence. The detector has an execution history storing unit with a plurality of entries and an address converter for converting an address of a memory access instruction into an entry number, where different addresses may be converted into entry numbers that are the same.
摘要翻译： 检测器检测由至少一个处理器执行的指令之间的地址中的至少一种依赖性，所述检测器被用于检测存在所述至少一种依赖性的可能性，其中如果存在所述至少一种依赖性 事实上，检测器检测到存在至少一种依赖性的可能性，并且如果实际上不存在至少一种依赖性，则检测器可以检测至少一种类型的伪随机 依赖。 检测器具有具有多个条目的执行历史存储单元和用于将存储器访问指令的地址转换为条目号的地址转换器，其中不同的地址可以被转换为相同的条目号。
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公开(公告)号：US06931514B2
公开(公告)日：2005-08-16
申请号：US09994806
申请日：2001-11-28
CPC分类号： G06F9/3834 , G06F9/3838 , G06F9/3842
摘要： A detector detects at least one kind of dependence in address between instructions executed by at least a processor, the detector being adopted to detect a possibility of presence of the at least one kind of dependence, wherein if the at least one kind of dependence is present in fact, then the detector detects a possibility of presence of the at least one kind of dependence, and if the at least one kind of dependence is not present in fact, then the detector may detect a pseudo presence of the at least one kind of dependence. The detector has an execution history storing unit with a plurality of entries and an address converter for converting an address of a memory access instruction into an entry number, where different addresses may be converted into entry numbers that are the same.
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6.发明授权Program parallelization device, program parallelization method, and program parallelization program 有权程序并行化设备，程序并行化方法和程序并行程序公开(公告)号：US07533375B2
公开(公告)日：2009-05-12
申请号：US10811925
申请日：2004-03-30
IPC分类号： G06F9/45
CPC分类号： G06F8/456
摘要： A control/data flow analysis unit analyzes the control flow and the data flow of a sequential processing program, and a fork point candidate determination unit determines fork point candidates taking this as the reference. A best fork point candidate combination determination unit determines the best fork point candidate combination by taking as the reference the result from the evaluation of the parallel execution performance of a test fork point candidate combination by a parallel execution performance evaluation unit, and a parallelized program output unit generates and outputs a parallelized program by inserting a fork command based on the best fork point candidate combination.
摘要翻译： 控制/数据流分析单元分析顺序处理程序的控制流程和数据流，叉点候选确定单元确定将其作为参考的叉点候选。 最佳叉点候选组合确定单元通过并行执行性能评估单元的并行执行性能评估单元的并行执行性能的评估的结果作为基准，来确定最佳叉点候选组合，并行程序输出 单元通过基于最佳叉点候选组合插入fork命令来生成并输出并行化程序。
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7.发明授权Data dependency detection using history table of entry number hashed from memory address 有权使用从存储器地址散列的入口号历史表的数据相关性检测公开(公告)号：US07418583B2
公开(公告)日：2008-08-26
申请号：US11126310
申请日：2005-05-11
IPC分类号： G06F9/34
CPC分类号： G06F9/3834 , G06F9/3838 , G06F9/3842
摘要： A detector detects at least one kind of dependence in address between instructions executed by at least a processor, the detector being adopted to detect a possibility of presence of the at least one kind of dependence, wherein if the at least one kind of dependence is present in fact, then the detector detects a possibility of presence of the at least one kind of dependence, and if the at least one kind of dependence is not present in fact, then the detector may detect a pseudo presence of the at least one kind of dependence. The detector has an execution history storing unit with a plurality of entries and an address converter for converting an address of a memory access instruction into an entry number, where different addresses may be converted into entry numbers that are the same.
摘要翻译： 检测器检测由至少一个处理器执行的指令之间的地址中的至少一种依赖性，所述检测器被用于检测存在所述至少一种依赖性的可能性，其中如果存在所述至少一种依赖性 事实上，检测器检测到存在至少一种依赖性的可能性，并且如果实际上不存在至少一种依赖性，则检测器可以检测至少一种类型的伪随机 依赖。 检测器具有具有多个条目的执行历史存储单元和用于将存储器访问指令的地址转换为条目号的地址转换器，其中不同的地址可以被转换为相同的条目号。
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公开(公告)号：US07243345B2
公开(公告)日：2007-07-10
申请号：US10189455
申请日：2002-07-08
申请人： Taku Ohsawa , Satoshi Matsushita
发明人： Taku Ohsawa , Satoshi Matsushita
CPC分类号： G06F9/4806 , G06F9/3009 , G06F9/3851
摘要： In a multi-thread executing method of dividing a single program into a plurality of threads and executing the program by a plurality of processors in parallel, at a time of every fork instruction of the executing thread, when there already exists a child thread generated form the above thread, the program cancels the child thread or makes invalid all the fork instructions other than the first fork instruction having succeeded in forking the child thread, hence to select one fork instruction for creating an effective child thread from a plurality of fork instructions existing within a parent thread, during the execution of the parent thread. Therefore, it can assure the Fork-Once limitation at a time of the program execution.
摘要翻译： 在将单个程序划分为多个线程并且由并行执行多个处理器执行程序的多线程执行方法中，在执行线程的每个fork指令时，当存在子线程生成形式时 在上述线程中，程序取消子线程，或使得第一叉指令之外的所有叉指令成功地无效，从而从存在的多个叉指令中选择用于创建有效子线程的一个叉指令 在父线程中，在执行父线程期间。 因此，可以在程序执行时确保“叉一次”限制。
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公开(公告)号：US07134124B2
公开(公告)日：2006-11-07
申请号：US10174953
申请日：2002-06-20
申请人： Taku Ohsawa , Satoshi Matsushita
发明人： Taku Ohsawa , Satoshi Matsushita
CPC分类号： G06F9/4806
摘要： Each processor comprises a register for storing start address of a forked child thread and a comparator for detecting that the value of its own program counter is coincident with the start address stored in this register. Each processor sends a thread stop notice to a thread controller when the value of its own program counter is coincident with the start address of the forked child thread and ends the execution of a parent thread when receiving a thread end permission from the thread controller.
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公开(公告)号：US07281250B2
公开(公告)日：2007-10-09
申请号：US10133409
申请日：2002-04-29
申请人： Taku Ohsawa , Satoshi Matsushita
发明人： Taku Ohsawa , Satoshi Matsushita
CPC分类号： G06F9/3851
摘要： With a single program divided into a plurality of threads A to C, at the execution of the threads in parallel to each other by a plurality of processors, determination is made of a forkability of a slave thread into other processor in response to a fork instruction in a master thread being executed by a predetermined processor and when forkable, the slave thread is forked into other processor and when not forkable, the fork instruction is invalidated to execute an instruction subsequent to the fork instruction by the predetermined processor and then execute a group of instructions of the slave thread by the predetermined processor.
摘要翻译： 通过分割成多个线程A到C的单个程序，在由多个处理器彼此并行执行线程时，响应于叉指令确定从线程到其他处理器的可分割性 在由预定处理器执行的主线程中，并且当叉形时，从线程被分叉到其他处理器中，并且当不可分叉时，叉指令无效以执行预定处理器之后的叉指令之后的指令，然后执行组 的预定处理器的从线程的指令。
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