公开(公告)号：US20080218287A1

公开(公告)日：2008-09-11

申请号：US12042445

申请日：2008-03-05

申请人： TAKUYA TAKAGI

发明人： TAKUYA TAKAGI

IPC分类号： H03H7/40

CPC分类号： H03H7/40 ,  H01L23/647 ,  H01L23/66 ,  H01L2924/0002 ,  H01L2924/19051 ,  H01L2924/3011 ,  H01L2924/00

摘要： An impedance adjusting circuit includes a semiconductor device accommodated in a semiconductor device case which has case pins and having a folded conductive line; an external reference resistor connected between a positive power supply line and a first one of the case pins, wherein a first line between the first case pin and the semiconductor device has a specific resistance; a first reference voltage generation resistor connected between the power supply line and a second one of the case pins; a second reference voltage generation resistor connected between the ground and a third one of the case pins; a resistance circuit comprising a second line between the second case pin and the folded conductive line and a third line between the third case pin and the folded conductive line, wherein a resistance between the second case pin and the third case pin is equal to the specific resistance; and a fourth line connected from the semiconductor device to the ground through the second reference voltage generation resistor and having a resistance equal to the specific resistance. The semiconductor device includes an adjusting circuit having a buffer and configured to adjust an output impedance of the buffer to be adaptive for a predetermined impedance.

摘要翻译： 阻抗调整电路包括容纳在具有外壳引脚并具有折叠导线的半导体器件壳体中的半导体器件; 连接在正电源线和第一壳体引脚之间的外部参考电阻，其中第一壳体引脚和半导体器件之间的第一线具有电阻率; 连接在电源线和第二个外壳销之间的第一参考电压产生电阻器; 第二参考电压产生电阻器，其连接在所述接地和所述壳体引脚中的第三个之间; 电阻电路，包括在第二外壳销和折叠导电线之间的第二线和第三外壳销和折叠导线之间的第三线，其中第二外壳销和第三外壳销之间的电阻等于具体 抵抗性; 以及通过第二参考电压产生电阻器从半导体器件连接到地并具有等于电阻率的电阻的第四线。 该半导体器件包括具有缓冲器并被配置为调整缓冲器的输出阻抗以适应预定阻抗的调整电路。

公开(公告)号：US07554417B2

公开(公告)日：2009-06-30

申请号：US12042445

申请日：2008-03-05

申请人： Takuya Takagi

发明人： Takuya Takagi

IPC分类号： H03H11/28

CPC分类号： H03H7/40 ,  H01L23/647 ,  H01L23/66 ,  H01L2924/0002 ,  H01L2924/19051 ,  H01L2924/3011 ,  H01L2924/00

摘要： An impedance adjusting circuit includes a semiconductor device accommodated in a semiconductor device case which has case pins and having a folded conductive line; an external reference resistor connected between a positive power supply line and a first one of the case pins, wherein a first line between the first case pin and the semiconductor device has a specific resistance; a first reference voltage generation resistor connected between the power supply line and a second one of the case pins; a second reference voltage generation resistor connected between the ground and a third one of the case pins; a resistance circuit comprising a second line between the second case pin and the folded conductive line and a third line between the third case pin and the folded conductive line, wherein a resistance between the second case pin and the third case pin is equal to the specific resistance; and a fourth line connected from the semiconductor device to the ground through the second reference voltage generation resistor and having a resistance equal to the specific resistance. The semiconductor device includes an adjusting circuit having a buffer and configured to adjust an output impedance of the buffer to be adaptive for a predetermined impedance.

摘要翻译： 阻抗调整电路包括容纳在具有外壳引脚并具有折叠导线的半导体器件壳体中的半导体器件; 连接在正电源线和第一壳体引脚之间的外部参考电阻，其中第一壳体引脚和半导体器件之间的第一线具有电阻率; 连接在电源线和第二个外壳销之间的第一参考电压产生电阻器; 第二参考电压产生电阻器，其连接在所述接地和所述壳体引脚中的第三个之间; 电阻电路，包括在第二外壳销和折叠导电线之间的第二线和第三外壳销和折叠导线之间的第三线，其中第二外壳销和第三外壳销之间的电阻等于具体 抵抗性; 以及通过第二参考电压产生电阻器从半导体器件连接到地并具有等于电阻率的电阻的第四线。 该半导体器件包括具有缓冲器并被配置为调整缓冲器的输出阻抗以适应预定阻抗的调整电路。

公开(公告)号：US06622686B2

公开(公告)日：2003-09-23

申请号：US09779630

申请日：2001-02-09

申请人： Takashi Komatsuda ,  Kaoru Aoki ,  Shinichi Takahashi ,  Takuya Takagi ,  Hiromu Nakamura ,  Tsutomu Yamasaki

发明人： Takashi Komatsuda ,  Kaoru Aoki ,  Shinichi Takahashi ,  Takuya Takagi ,  Hiromu Nakamura ,  Tsutomu Yamasaki

IPC分类号： F02F124

CPC分类号： F02F1/4214 ,  F02F2001/245

摘要： In a cylinder head 1 of an internal combustion engine, communicating passageways 17, 18, 17′, 18′ for coolant are provided between combustion chambers 3 and pass-through holes 21 to 28 at positions which overlap straight lines L1, L2 connecting centers C2, C3 of the exhaust port openings 6a, 7a with centers C5 to C8 of the pass-through holes 25 to 28 and straight lines L3, L4 connecting centers C9, C10 of the intake port openings 4a, 5a with centers C11 to c14 of the pass-through holes 21 to 24 when a mating surface 2 of the cylinder head 1 with the cylinder block is viewed from the bottom. When peripheries of the exhaust port openings 6a, 7a and intake port openings 4a, 5a thermally expand, the suppression of thermal expansion by the bolts at fastening portions is alleviated by the communicating passageways 17, 18, 17′, 18′.

摘要翻译： 在内燃机的气缸盖1中，用于冷却剂的连通通道17,18,17'，18'设置在燃烧室3和穿通孔21至28之间的重叠直线L1，L2连接中心C2 具有通孔25至28的中心C5至C8的排气口开口6a，7a和进气口开口4a，5a的连接中心C9，C10的直线L3，L4与中心C11至c14的排气口开口6a，7a的C3 当从底部观察气缸盖1的与气缸体的配合表面2时的通孔21至24。 当排气口开口6a，7a和进气口开口4a，5a的周边热膨胀时，通过连通通道17,18,17'，18'减轻了紧固部分处的螺栓对热膨胀的抑制。

公开(公告)号：US20060197568A1

公开(公告)日：2006-09-07

申请号：US11362819

申请日：2006-02-28

申请人： Takuya Takagi

发明人： Takuya Takagi

IPC分类号： H03K5/12

CPC分类号： H03K5/01

摘要： A slew rate calibrating circuit and a slew rate calibrating method are provided which are capable of adjusting, with high accuracy, a slew rate of a signal to be output to a transmission path. A first clock is input and a delay time of a variable delay circuit is increased or decreased so that a phase of the first clock coincides with a phase of a first differential buffer output signal which rises when a voltage of a transmission path outgoing signal is at the same level as a first reference voltage or exceeds the first reference voltage. Then, a second clock is input and a slew rate of an output buffer is increased or decreased so that a phase of the second clock coincides with a phase of a second differential buffer output signal which rises when a voltage of a transmission path output signal is at the same level as a second reference voltage or exceeds the second reference voltage.

摘要翻译： 提供了一种压摆率校准电路和压摆率校准方法，其能够高精度地调整要输出到传输路径的信号的转换速率。 第一时钟被输入，并且可变延迟电路的延迟时间被增加或减小，使得第一时钟的相位与当传输路径输出信号的电压处于时的上升的第一差分缓冲器输出信号的相位一致 与第一参考电压相同或超过第一参考电压。 然后，输入第二时钟，并且输出缓冲器的转换速率被增加或减小，使得第二时钟的相位与当传输路径输出信号的电压为（...）时上升的第二差分缓冲器输出信号的相位一致 在与第二参考电压相同的电平或超过第二参考电压。

公开(公告)号：US07288958B2

公开(公告)日：2007-10-30

申请号：US11362819

申请日：2006-02-28

申请人： Takuya Takagi

发明人： Takuya Takagi

IPC分类号： H03K3/017 ,  H03K5/12 ,  H03K5/02 ,  H03K17/16

CPC分类号： H03K5/01

摘要： A slew rate calibrating circuit and a slew rate calibrating method are provided which are capable of adjusting, with high accuracy, a slew rate of a signal to be output to a transmission path. A first clock is input and a delay time of a variable delay circuit is increased or decreased so that a phase of the first clock coincides with a phase of a first differential buffer output signal which rises when a voltage of a transmission path outgoing signal is at the same level as a first reference voltage or exceeds the first reference voltage. Then, a second clock is input and a slew rate of an output buffer is increased or decreased so that a phase of the second clock coincides with a phase of a second differential buffer output signal which rises when a voltage of a transmission path output signal is at the same level as a second reference voltage or exceeds the second reference voltage.

摘要翻译： 提供了一种压摆率校准电路和压摆率校准方法，其能够高精度地调整要输出到传输路径的信号的转换速率。 第一时钟被输入，并且可变延迟电路的延迟时间被增加或减小，使得第一时钟的相位与当传输路径输出信号的电压处于时的上升的第一差分缓冲器输出信号的相位一致 与第一参考电压相同或超过第一参考电压。 然后，输入第二时钟，并且输出缓冲器的转换速率被增加或减小，使得第二时钟的相位与当传输路径输出信号的电压为（...）时上升的第二差分缓冲器输出信号的相位一致 在与第二参考电压相同的电平或超过第二参考电压。