公开(公告)号：US08477535B2

公开(公告)日：2013-07-02

申请号：US13180189

申请日：2011-07-11

申请人： Tamiyu Kato

发明人： Tamiyu Kato

IPC分类号： G11C16/04

CPC分类号： G11C16/344 ,  G11C16/3445

摘要： A semiconductor device is provided which comprises a nonvolatile memory capable of storing complementary data and performing a more accurate blank check than ever before.A nonvolatile memory comprises a memory array having a plurality of twin cells arranged therein for storing complementary data, and first to third determination units. The first determination unit determines, for each of the twin cells selected by a selection circuit, whether or not a first condition that the threshold voltage of one memory cell is higher than a reference value commonly set and the threshold voltage of the other memory cell is lower than the reference value is satisfied. The second determination unit determines whether or not a second condition that all the selected twin cells satisfy the first condition is satisfied. The third determination unit determines, based on the determination result of the second determination unit, whether or not each of the selected twin cells is in a blank state.

摘要翻译： 提供了一种半导体器件，其包括能够存储补充数据并执行比以前更准确的空白检查的非易失性存储器。 非易失性存储器包括存储器阵列，其具有布置在其中的用于存储补充数据的多个双胞胎，以及第一至第三确定单元。 第一确定单元对于由选择电路选择的每个双胞胎单元确定一个存储单元的阈值电压是否高于共同设定的基准值的第一条件和另一个存储单元的阈值电压是否为 低于参考值即可。 第二确定单元确定是否满足所有所选择的双胞胎满足第一条件的第二条件。 第三确定单元基于第二确定单元的确定结果确定所选择的双胞胎单元是否处于空白状态。

公开(公告)号：US20150301935A1

公开(公告)日：2015-10-22

申请号：US14382159

申请日：2012-03-02

申请人： Tamiyu KATO ,  Yukiko MARUYAMA ,  Shinya IZUMI ,  Kiyoshi NAKAKIMURA ,  Yoshihiro SEGUCHI

发明人： Tamiyu KATO ,  Yukiko MARUYAMA ,  Shinya IZUMI ,  Kiyoshi NAKAKIMURA ,  Yoshihiro SEGUCHI

IPC分类号： G06F12/02

CPC分类号： G06F12/0246 ,  G06F9/30065 ,  G06F9/324 ,  G06F2212/7208

摘要： A program counter (12) updates an address by adding a first value or a second value. A code select circuit (14) selects, in accordance with the address of the program counter (12), one of an insert code retained in an insert code register set block (17) and corresponding to the address specified by the program counter (12), and an original code stored in a flash control code ROM (13) and having the address specified by the program counter (12). An instruction execution unit (15) executes the selected code. At least one of a plurality of original codes and the insert code is a multicycle instruction. The program counter (14) stops update of the address when the multicycle instruction is executed.

摘要翻译： 程序计数器（12）通过添加第一值或第二值来更新地址。 代码选择电路（14）根据程序计数器（12）的地址选择保存在插入代码寄存器设置块（17）中并与程序计数器（12）指定的地址相对应的插入代码 ）和存储在闪存控制代码ROM（13）中并具有由程序计数器（12）指定的地址的原始代码。 指令执行单元（15）执行所选择的代码。 多个原始代码和插入代码中的至少一个是多周期指令。 当执行多周期指令时，程序计数器（14）停止更新地址。

公开(公告)号：US09436598B2

公开(公告)日：2016-09-06

申请号：US14003100

申请日：2011-03-04

申请人： Tamaki Tsuruda ,  Tamiyu Kato

发明人： Tamaki Tsuruda ,  Tamiyu Kato

IPC分类号： G06F12/00 ,  G06F12/02 ,  G11C16/22

CPC分类号： G06F12/0246 ,  G11C16/225

摘要： In an internal register, a value for controlling operation of a flash memory is stored. A power shutoff detection register holds a value which changes when power shutoff occurs, and data stored in a specific memory cell is written in the power shutoff detection register. An EX-OR circuit compares the data stored in the specific memory cell with the value of the power shutoff detection register to thereby detect power shutoff. When power shutoff is detected, the value of the internal register is re-set. Thus, when power shutoff occurs, the flash memory can be prevented from malfunctioning.

摘要翻译： 在内部寄存器中，存储用于控制闪速存储器的操作的值。 电源关闭检测寄存器保存发生电源关闭时变化的值，存储在特定存储单元中的数据写入电源关闭检测寄存器。 EX-OR电路将存储在特定存储单元中的数据与功率关闭检测寄存器的值进行比较，从而检测电源关闭。 当检测到电源关闭时，内部寄存器的值被重新设置。 因此，当发生电源关闭时，可以防止闪存发生故障。

公开(公告)号：US06515900B2

公开(公告)日：2003-02-04

申请号：US09832986

申请日：2001-04-12

申请人： Tamiyu Kato ,  Tomoshi Futatsuya ,  Yoshikazu Miyawaki

发明人： Tamiyu Kato ,  Tomoshi Futatsuya ,  Yoshikazu Miyawaki

IPC分类号： G11C1134

CPC分类号： G11C16/26 ,  G11C16/08 ,  G11C16/20 ,  G11C2216/22

摘要： A non-volatile semiconductor memory device includes a bank pointer, in which a signal for designating an operating mode to be performed is generated according to coincidence/non-coincidence of prescribed bits of address signals supplied from an address buffer, and the generated signal is supplied to an internal control circuit. Thus, necessary data can be read out from the non-volatile semiconductor memory device at high speed, so that usability of the device is improved.

摘要翻译： 非易失性半导体存储器件包括存储体指针，其中根据从地址缓冲器提供的地址信号的规定位的一致/非重合，生成用于指定要执行的操作模式的信号，并且所生成的信号为 提供给内部控制电路。 因此，可以高速地从非易失性半导体存储器件读出必要的数据，从而提高了器件的可用性。

公开(公告)号：US20130339590A1

公开(公告)日：2013-12-19

申请号：US14003100

申请日：2011-03-04

申请人： Tamaki Tsuruda ,  Tamiyu Kato

发明人： Tamaki Tsuruda ,  Tamiyu Kato

IPC分类号： G06F12/02

CPC分类号： G06F12/0246 ,  G11C16/225

摘要： In an internal register, a value for controlling operation of a flash memory is stored. A power shutoff detection register holds a value which changes when power shutoff occurs, and data stored in a specific memory cell is written in the power shutoff detection register. An EX-OR circuit compares the data stored in the specific memory cell with the value of the power shutoff detection register to thereby detect power shutoff. When power shutoff is detected, the value of the internal register is re-set. Thus, when power shutoff occurs, the flash memory can be prevented from malfunctioning.

摘要翻译： 在内部寄存器中，存储用于控制闪速存储器的操作的值。 电源关闭检测寄存器保存发生电源关闭时变化的值，存储在特定存储单元中的数据写入电源关闭检测寄存器。 EX-OR电路将存储在特定存储单元中的数据与功率关闭检测寄存器的值进行比较，从而检测电源关闭。 当检测到电源关闭时，内部寄存器的值被重新设置。 因此，当发生电源关闭时，可以防止闪存发生故障。

公开(公告)号：US20120033495A1

公开(公告)日：2012-02-09

申请号：US13180189

申请日：2011-07-11

申请人： Tamiyu KATO

发明人： Tamiyu KATO

IPC分类号： G11C16/34 ,  G11C16/04

CPC分类号： G11C16/344 ,  G11C16/3445

摘要： A semiconductor device is provided which comprises a nonvolatile memory capable of storing complementary data and performing a more accurate blank check than ever before.A nonvolatile memory comprises a memory array having a plurality of twin cells arranged therein for storing complementary data, and first to third determination units. The first determination unit determines, for each of the twin cells selected by a selection circuit, whether or not a first condition that the threshold voltage of one memory cell is higher than a reference value commonly set and the threshold voltage of the other memory cell is lower than the reference value is satisfied. The second determination unit determines whether or not a second condition that all the selected twin cells satisfy the first condition is satisfied. The third determination unit determines, based on the determination result of the second determination unit, whether or not each of the selected twin cells is in a blank state.

摘要翻译： 提供了一种半导体器件，其包括能够存储补充数据并执行比以前更准确的空白检查的非易失性存储器。 非易失性存储器包括存储器阵列，其具有布置在其中的用于存储补充数据的多个双胞胎，以及第一至第三确定单元。 第一确定单元对于由选择电路选择的每个双胞胎单元确定一个存储单元的阈值电压是否高于共同设定的基准值的第一条件和另一个存储单元的阈值电压是否为 低于参考值即可。 第二确定单元确定是否满足所有所选择的双胞胎满足第一条件的第二条件。 第三确定单元基于第二确定单元的确定结果确定所选择的双胞胎单元是否处于空白状态。