公开(公告)号：US09035602B2

公开(公告)日：2015-05-19

申请号：US13594673

申请日：2012-08-24

Applicant: Tao Jing

Inventor： Tao Jing

IPC: H02J7/00 ,  H02J7/02 ,  H02J5/00

CPC classification number: H02J7/0044 ,  H02J5/005 ,  H02J7/0034 ,  H02J7/0036 ,  H02J7/02 ,  H02J7/025

Abstract: A wireless direct contact charger includes (a) a voltage supply; (b) a first plate electrode and a second plate electrode; (c) a polarity detection circuit that detects; and (d) a switching circuit. When the first electrode or the second electrode of the portable device is placed on the first plate electrode or the second plate electrode, the polarity detection circuit detects the polarity of the portable device charging terminals (i.e, whether the first electrode of the portable device is in contact with the first plate electrode, the second electrode of the portable device is in contact with the first plate electrode or any other suitable orientations). Based on the detected polarity, the switching circuit connects the first plate electrode and the second plate electrode to the voltage supply to provide an output voltage to the portable device for charging its battery.

Abstract translation: 无线直接接触充电器包括（a）电压源; （b）第一板电极和第二板电极; （c）极性检测电路，其检测; 和（d）开关电路。 当便携式设备的第一电极或第二电极被放置在第一平板电极或第二平板电极上时，极性检测电路检测便携式设备充电端子的极性（即便携式设备的第一电极是否为 与第一平板电极接触，便携式设备的第二电极与第一平板电极或任何其它合适的取向接触）。 基于检测到的极性，开关电路将第一板电极和第二板电极连接到电压源，以向便携式设备提供输出电压以对其电池充电。

公开(公告)号：US08963527B2

公开(公告)日：2015-02-24

申请号：US12983288

申请日：2010-12-31

Applicant: Tao Jing

Inventor： Tao Jing

IPC: H02M1/44

CPC classification number: H02M1/44

Abstract: The present invention provides for EMI mitigation in switching circuitry, such as power converters, by implementing a controlled, non-random change in frequency in every cycle of switch control signals based on a static or dynamically changing modulation cycle. This permits frequency spreading across a wide range while avoiding excessive jitter between cycles and voltage dropouts common to randomized EMI control circuitry. Further, since it may be implemented digitally, some embodiments may avoid performance, size and power consumption problems experienced by mixed signal or analog switch control circuitry and EMI control circuitry. Further still, implementations of the present invention may mitigate EMI from a constant frequency source without the necessity of a variable frequency source, such as one generated by a VCO, to realize frequency variation. By eliminating the need for analog and mixed signal circuitry, and additional corrective circuitry, some embodiments may also reduce design, testing and production costs.

Abstract translation: 本发明通过基于静态或动态变化的调制周期在开关控制信号的每个周期中实现频率的受控非随机变化来提供诸如功率转换器的开关电路中的EMI抑制。 这允许在宽范围内进行频率扩展，同时避免了随机EMI控制电路共同的周期和电压下降之间的过度抖动。 此外，由于可以数字地实现，一些实施例可以避免混合信号或模拟开关控制电路和EMI控制电路经历的性能，尺寸和功耗问题。 此外，本发明的实施方式可以从恒定频率源减轻EMI，而不需要诸如VCO产生的可变频率源来实现频率变化。 通过消除对模拟和混合信号电路以及附加校正电路的需要，一些实施例还可以降低设计，测试和生产成本。

公开(公告)号：US20130132340A1

公开(公告)日：2013-05-23

申请号：US13813027

申请日：2011-08-01

Applicant: Tao Jing ,  Haibin Ke

Inventor： Tao Jing ,  Haibin Ke

IPC: G06F17/30

CPC classification number: G06F17/30174 ,  G06F17/30144

Abstract: The present invention provides a file synchronization method, an electronic device and a synchronization system. The method comprises: in a hybrid system having a first system and a second system, monitoring in the first system a first cache of the first system, in which first data corresponding to a first file stored in a non-volatile storage of the first system opened by a first file processing program of the first system is saved; sending, to the second system, operating content performed by the first file processing program on the first file via a data information channel between the first system and the second system, when the first data in the first cache is changed; wherein a second file processing program in the second system performs a synchronization processing on a second file according to the operating content, the second file being a file corresponding to the first file in the second system. With the above technical solutions, a real-time synchronization/updating may be performed on same files in different systems, since the plug-in application service logic is provided and may access the cache in real time.

Abstract translation: 本发明提供一种文件同步方法，电子装置和同步系统。 该方法包括：在具有第一系统和第二系统的混合系统中，在第一系统中监视第一系统的第一高速缓存，其中第一数据对应于存储在第一系统的非易失性存储器中的第一文件 由第一个系统的第一个文件处理程序打开保存; 当所述第一高速缓存中的所述第一数据被改变时，经由所述第一系统和所述第二系统之间的数据信息通道向所述第二系统发送由所述第一文件处理程序执行的所述第一文件处理程序的操作; 其中所述第二系统中的第二文件处理程序根据所述操作内容对第二文件执行同步处理，所述第二文件是与所述第二系统中的所述第一文件相对应的文件。 利用上述技术方案，可以对不同系统中的相同文件进行实时同步/更新，因为提供了插件应用服务逻辑，并可实时访问高速缓存。

公开(公告)号：US07903380B2

公开(公告)日：2011-03-08

申请号：US12256643

申请日：2008-10-23

Applicant: Tao Jing ,  Maidong Dai

Inventor： Tao Jing ,  Maidong Dai

IPC: H02H3/22

CPC classification number: H02H9/046 ,  H02H3/44

Abstract: An electrostatic discharge (ESD) protection circuit configured completely inside one of a power pad and an I/O pad of an electronic circuit, the ESD protection circuit comprising an electrostatic discharge (ESD) circuit that, when activated, discharges an ESD from a first voltage bus to a second voltage bus. The second voltage bus is at a lower electrical potential than the first voltage bus. An ESD discharge control circuit in electrical connection with the ESD discharge circuit that controls the activation of the ESD discharge circuit and including an NMOS transistor and an electrical node. The NMOS transistor regulating a rate of voltage decay of the electrical node from a predetermined high voltage level to a lower voltage level, the regulation of the rate of voltage decay of the electrical node is non-linear. The activation of the ESD discharge circuit determined by the rate of voltage decay of the electrical node.

Abstract translation: 一种静电放电（ESD）保护电路，其完全配置在电子电路的电源焊盘和I / O焊盘之一内，所述ESD保护电路包括静电放电（ESD）电路，其在被激活时从第一 电压总线到第二电压总线。 第二电压总线处于比第一电压总线更低的电位。 与ESD放电电路电连接的ESD放电控制电路，其控制ESD放电电路的激活并且包括NMOS晶体管和电节点。 NMOS晶体管将电节点的电压衰减速率从预定的高电压电平调节到较低的电压电平，电节点的电压衰减速率的调节是非线性的。 ESD放电电路的激活由电节点的电压衰减速率决定。

公开(公告)号：US07567100B2

公开(公告)日：2009-07-28

申请号：US11694861

申请日：2007-03-30

Applicant: Tao Jing

Inventor： Tao Jing

IPC: H03L7/06

CPC classification number: H03L7/06 ,  H03L7/143

Abstract: An apparatus is provided for detecting the loss of an input clock signal for a phase-locked loop (PLL). The apparatus includes a time delay circuit, a first frequency divider and a digital logic circuit. The time delay circuit receives the input clock signal and outputs a first time-delayed clock signal. The first frequency divider receives an input signal from an internal clock of the PLL and outputs a clock signal having the same frequency or a lower frequency than that of the time-delayed clock signal. The digital logic circuit that receives the first frequency divider output signal and the first time-delayed clock signal and outputs a signal indicating the loss of the input clock signal if there is no first time-delayed clock signal for a cycle of the first frequency divider output signal.

Abstract translation: 提供了一种用于检测锁相环（PLL）的输入时钟信号的损耗的装置。 该装置包括时延电路，第一分频器和数字逻辑电路。 时间延迟电路接收输入时钟信号并输出​​第一时间延迟的时钟信号。 第一分频器从PLL的内部时钟接收输入信号，并输出具有与时间延迟的时钟信号相同频率或更低频率的时钟信号。 数字逻辑电路，其接收第一分频器输出信号和第一时间延迟时钟信号，并且如果没有用于第一分频器的周期的第一时间延迟时钟信号，则输出指示输入时钟信号丢失的信号 输出信号。

公开(公告)号：US09361309B2

公开(公告)日：2016-06-07

申请号：US13813027

申请日：2011-08-01

Applicant: Tao Jing ,  Haibin Ke

Inventor： Tao Jing ,  Haibin Ke

IPC: G06F7/00 ,  G06F17/30

CPC classification number: G06F17/30174 ,  G06F17/30144

Abstract: The present invention provides a file synchronization method, an electronic device and a synchronization system. Operating content performed on a first file in a first system is sent to a second system via a data information channel between the first system and the second system when the first file is changed. A second file processing program in the second system performs a synchronization processing on a second file according to the operating content, the second file being a file corresponding to the first file in the second system. With the above technical solutions, a real-time synchronization/updating may be performed on same files in different systems.

Abstract translation: 本发明提供一种文件同步方法，电子装置和同步系统。 当第一文件被改变时，在第一系统中的第一文件上执行的操作内容经由第一系统和第二系统之间的数据信息通道发送到第二系统。 第二系统中的第二文件处理程序根据操作内容对第二文件执行同步处理，第二文件是与第二系统中的第一文件相对应的文件。 利用上述技术方案，可以对不同系统中的相同文件执行实时同步/更新。

公开(公告)号：US20140055078A1

公开(公告)日：2014-02-27

申请号：US13594673

申请日：2012-08-24

Applicant: Tao Jing

Inventor： Tao Jing

IPC: H02J7/00

CPC classification number: H02J7/0044 ,  H02J5/005 ,  H02J7/0034 ,  H02J7/0036 ,  H02J7/02 ,  H02J7/025

Abstract: A wireless direct contact charger includes (a) a voltage supply; (b) a first plate electrode and a second plate electrode; (c) a polarity detection circuit that detects; and (d) a switching circuit. When the first electrode or the second electrode of the portable device is placed on the first plate electrode or the second plate electrode, the polarity detection circuit detects the polarity of the portable device charging terminals (i.e, whether the first electrode of the portable device is in contact with the first plate electrode, the second electrode of the portable device is in contact with the first plate electrode or any other suitable orientations). Based on the detected polarity, the switching circuit connects the first plate electrode and the second plate electrode to the voltage supply to provide an output voltage to the portable device for charging its battery,

Abstract translation: 无线直接接触充电器包括（a）电压源; （b）第一板电极和第二板电极; （c）极性检测电路，其检测; 和（d）开关电路。 当便携式设备的第一电极或第二电极被放置在第一平板电极或第二平板电极上时，极性检测电路检测便携式设备充电端子的极性（即便携式设备的第一电极是否为 与第一平板电极接触，便携式设备的第二电极与第一平板电极或任何其它合适的取向接触）。 基于检测到的极性，开关电路将第一板电极和第二板电极连接到电压源，以向便携式设备提供输出电压以对其电池充电，

公开(公告)号：US20120221870A1

公开(公告)日：2012-08-30

申请号：US13259838

申请日：2010-12-29

Applicant: Qian Zhao ,  Bin Li ,  Tao Jing

Inventor： Qian Zhao ,  Bin Li ,  Tao Jing

IPC: G06F1/28

CPC classification number: G06F1/1654 ,  G06F1/3218 ,  G06F1/3265 ,  G06F1/3287 ,  G06F21/84 ,  Y02D10/171 ,  Y02D50/20

Abstract: A computer and a method for controlling an operating state of a device thereof are disclosed. The method comprises: detecting that a display portion and a host portion of the computer are in a state of being disconnected from each other; and generating a state event or a control instruction corresponding to the disconnected state for switching the device to an inactive state. With the present invention, when the state of a computer changes, e.g., when a display portion and a host portion of a portable computer are separated, an operating system can control a device to switch its operating state, e.g., deactivate the device, based on a generated state event. In this way, it is possible to avoid unnecessary power consumption of the entire computer due to the active state of the device, and any potential security risk can be eliminated.

Abstract translation: 公开了一种用于控制其装置的操作状态的计算机和方法。 该方法包括：检测计算机的显示部分和主机部分处于彼此断开的状态; 以及产生与所述断开状态相对应的状态事件或控制指令，以将所述设备切换到非活动状态。 利用本发明，当计算机的状态改变时，例如当便携式计算机的显示部分和主机部分分开时，操作系统可以控制设备切换其操作状态，例如基于设备的停用 在生成的状态事件。 以这种方式，由于设备的活动状态，可以避免整个计算机的不必要的电力消耗，并且可以消除任何潜在的安全风险。

公开(公告)号：US20090256600A1

公开(公告)日：2009-10-15

申请号：US12488989

申请日：2009-06-22

Applicant: Tao Jing

Inventor： Tao Jing

IPC: H03L7/06

CPC classification number: H03L7/06 ,  H03L7/143

Abstract: An apparatus is provided for detecting the loss of an input clock signal for a phase-locked loop (PLL). The apparatus includes a time delay circuit, a first frequency divider and a digital logic circuit. The time delay circuit receives the input clock signal and outputs a first time-delayed clock signal. The first frequency divider receives an input signal from an internal clock of the PLL and outputs a clock signal having the same frequency or a lower frequency than that of the time-delayed clock signal. The digital logic circuit that receives the first frequency divider output signal and the first time-delayed clock signal and outputs a signal indicating the loss of the input clock signal if there is no first time-delayed clock signal for a cycle of the first frequency divider output signal.

Abstract translation: 提供了一种用于检测锁相环（PLL）的输入时钟信号的损耗的装置。 该装置包括时延电路，第一分频器和数字逻辑电路。 时间延迟电路接收输入时钟信号并输出​​第一时间延迟的时钟信号。 第一分频器从PLL的内部时钟接收输入信号，并输出具有与时间延迟的时钟信号相同频率或更低频率的时钟信号。 数字逻辑电路，其接收第一分频器输出信号和第一时间延迟时钟信号，并且如果没有用于第一分频器的周期的第一时间延迟时钟信号，则输出指示输入时钟信号丢失的信号 输出信号。

公开(公告)号：US06350979B1

公开(公告)日：2002-02-26

申请号：US09301428

申请日：1999-04-28

Applicant: Tao Jing

Inventor： Tao Jing

IPC: H01L2700

CPC classification number: H01L27/14812

Abstract: An image sensor integrated circuit with a pixel cell having photogates wherein each photogate has a number of gaps which allow light to penetrate to the substrate. The gaps are open in the direction of the floating diffusion, in order to minimize the trapping of charges. In a preferred embodiment, the floating gate has a comb structure, with the tines of the comb extending toward the floating gate. Preferably, the tines or fingers are wider than the gaps. In a preferred embodiment, the gaps are no wider than 3 microns.

Abstract translation: 一种具有像素单元的图像传感器集成电路，具有摄影门，其中每个光栅具有允许光穿透至基板的多个间隙。 间隙在浮动扩散的方向上是开放的，以便最小化电荷的捕获。 在优选实施例中，浮动栅极具有梳状结构，其中梳子的尖齿朝向浮动栅极延伸。 优选地，尖齿或手指比间隙宽。 在优选实施例中，间隙不大于3微米。