公开(公告)号：US08611216B2

公开(公告)日：2013-12-17

申请号：US13250765

申请日：2011-09-30

申请人： Dennis C. Ferguson ,  Philippe Lacroute ,  Chi-Chung Chen ,  Gerald Cheung ,  Tatao Chuang ,  Pankaj Patel ,  Viswesh Ananthakrishnan

发明人： Dennis C. Ferguson ,  Philippe Lacroute ,  Chi-Chung Chen ,  Gerald Cheung ,  Tatao Chuang ,  Pankaj Patel ,  Viswesh Ananthakrishnan

IPC分类号： H04J1/16 ,  H04L12/66 ,  H04L12/28

CPC分类号： H04L49/90 ,  H04L47/50 ,  H04L47/6225 ,  H04L49/3036 ,  H04L49/351 ,  H04L49/901 ,  H04L49/9094

摘要： Ordering logic ensures that data items being processed by a number of parallel processing units are unloaded from the processing units in the original per-flow order that the data items were loaded into the parallel processing units. The ordering logic includes a pointer memory, a tail vector, and a head vector. Through these three elements, the ordering logic keeps track of a number of “virtual queues” corresponding to the data flows. A round robin arbiter unloads data items from the processing units only when a data item is at the head of its virtual queue.

摘要翻译： 订购逻辑确保由多个并行处理单元处理的数据项以原始每流顺序从处理单元卸载，数据项被加载到并行处理单元中。 排序逻辑包括指针存储器，尾部矢量和头部矢量。 通过这三个元素，排序逻辑跟踪与数据流相对应的多个“虚拟队列”。 循环仲裁器只有在数据项位于其虚拟队列的头部时才从处理单元中卸载数据项。

公开(公告)号：US07764606B1

公开(公告)日：2010-07-27

申请号：US11755292

申请日：2007-05-30

申请人： Dennis C. Ferguson ,  Philippe Lacroute ,  Chi-Chung Chen ,  Gerald Cheung ,  Tatao Chuang ,  Pankaj Patel ,  Viswesh Ananthakrishnan

发明人： Dennis C. Ferguson ,  Philippe Lacroute ,  Chi-Chung Chen ,  Gerald Cheung ,  Tatao Chuang ,  Pankaj Patel ,  Viswesh Ananthakrishnan

IPC分类号： H04L1/00 ,  H04L12/56 ,  H04L12/28

CPC分类号： H04L49/90 ,  H04L47/50 ,  H04L47/6225 ,  H04L49/3036 ,  H04L49/351 ,  H04L49/901 ,  H04L49/9094

摘要： Ordering logic ensures that data items being processed by a number of parallel processing units are unloaded from the processing units in the original per-flow order that the data items were loaded into the parallel processing units. The ordering logic includes a pointer memory, a tail vector, and a head vector. Through these three elements, the ordering logic keeps track of a number of “virtual queues” corresponding to the data flows. A round robin arbiter unloads data items from the processing units only when a data item is at the head of its virtual queue.

摘要翻译： 订购逻辑确保由多个并行处理单元处理的数据项以原始每流顺序从处理单元卸载，数据项被加载到并行处理单元中。 排序逻辑包括指针存储器，尾部矢量和头部矢量。 通过这三个元素，排序逻辑跟踪与数据流相对应的多个“虚拟队列”。 循环仲裁器只有在数据项位于其虚拟队列的头部时才从处理单元中卸载数据项。

公开(公告)号：US07009416B1

公开(公告)日：2006-03-07

申请号：US09984325

申请日：2001-10-29

申请人： Tatao Chuang ,  Devereaux C. Chen

发明人： Tatao Chuang ,  Devereaux C. Chen

IPC分类号： G01R31/02 ,  G01R31/26

CPC分类号： G01R31/3177

摘要： A system for monitoring internal states of an integrated circuit includes logic nodes, selection logic and a monitor unit. The logic nodes are disposed within the integrated circuit and the selection logic is coupled to monitor pins externally accessible on the integrated circuit. The selection logic retrieves internal states of select logic nodes based on signals applied via the monitor pins. The monitor unit reads the internal states of the select logic nodes via the monitor pins.

摘要翻译： 用于监视集成电路的内部状态的系统包括逻辑节点，选择逻辑和监视器单元。 逻辑节点设置在集成电路内，并且选择逻辑耦合到集成电路上外部可访问的监视引脚。 选择逻辑基于通过监视器引脚施加的信号来检索选择逻辑节点的内部状态。 监视器单元通过监视器引脚读取选择逻辑节点的内部状态。

公开(公告)号：US06233721B1

公开(公告)日：2001-05-15

申请号：US09270738

申请日：1999-03-16

申请人： Chong Ming Lin ,  Tatao Chuang ,  Tran Long ,  Hy Hoang

发明人： Chong Ming Lin ,  Tatao Chuang ,  Tran Long ,  Hy Hoang

IPC分类号： G06F1500

CPC分类号： H01L23/5286 ,  G06F17/5068 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method for manufacturing a power bus on a chip, where the power bus has slits generated therein. The present invention relates to a method to manufacture a power bus in which the reference to a layout data base shows the coordinate location of the power buses in the chip. A height and width for the power bus is calculated based on its coordinates. Based on the height and width of the power buses and the predetermined size and spacing between power slits, a number of power slits to be generated is determined. These power slits are then generated by adding the power slits to the power bus in the coordinates of the layout database. The method of the present invention also generates power slits for use in manufacturing power buses on a chip for cases in which the power buses overlap.

摘要翻译： 一种在芯片上制造电力总线的方法，其中电源总线上产生狭缝。 本发明涉及一种制造电源总线的方法，其中对布线数据库的参考表示芯片中电源总线的坐标位置。 电源总线的高度和宽度根据其坐标进行计算。 基于电源总线的高度和宽度以及功率狭缝之间的预定尺寸和间隔，确定要产生的多个功率狭缝。 然后通过在布局数据库的坐标中将功率狭缝添加到电源总线来产生这些功率狭缝。 本发明的方法还产生用于在电源总线重叠的情况下制造芯片上的电源总线的电源插槽。

公开(公告)号：US07516436B2

公开(公告)日：2009-04-07

申请号：US11483638

申请日：2006-07-11

申请人： Chong Ming Lin ,  Tatao Chuang ,  Tran Long ,  Hy Hoang

发明人： Chong Ming Lin ,  Tatao Chuang ,  Tran Long ,  Hy Hoang

IPC分类号： G06F17/50

CPC分类号： H01L23/5286 ,  G06F17/5068 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method for manufacturing a power bus on a chip, where the power bus has slits generated therein. The present invention relates to a method to manufacture a power bus in which the reference to a layout data base shows the coordinate location of the power buses in the chip. A height and width for the power bus is calculated based on its coordinates. Based on the height and width of the power buses and the predetermined size and spacing between power slits, a number of power slits to be generated is determined. These power slits are then generated by adding the power slits to the power bus in the coordinates of the layout database. The method of the present invention also generates power slits for use in manufacturing power buses on a chip for cases in which the power buses overlap.

摘要翻译： 一种在芯片上制造电力总线的方法，其中电源总线上产生狭缝。 本发明涉及一种制造电源总线的方法，其中参考布局数据库显示芯片中电源总线的坐标位置。 电源总线的高度和宽度根据其坐标进行计算。 基于电源总线的高度和宽度以及功率狭缝之间的预定尺寸和间隔，确定要产生的多个功率狭缝。 然后通过在布局数据库的坐标中将功率狭缝添加到电源总线来产生这些功率狭缝。 本发明的方法还产生用于在电源总线重叠的情况下制造芯片上的电源总线的电源插槽。

公开(公告)号：US07289503B1

公开(公告)日：2007-10-30

申请号：US10206999

申请日：2002-07-30

申请人： Pradeep Sindhu ,  Debashis Basu ,  Pankaj Patel ,  Raymond Lim ,  Avanindra Godbole ,  Tatao Chuang ,  Chi-Chung K. Chen ,  Jeffrey G. Libby ,  Dennis Ferguson ,  Philippe Lacroute ,  Gerald Cheung

发明人： Pradeep Sindhu ,  Debashis Basu ,  Pankaj Patel ,  Raymond Lim ,  Avanindra Godbole ,  Tatao Chuang ,  Chi-Chung K. Chen ,  Jeffrey G. Libby ,  Dennis Ferguson ,  Philippe Lacroute ,  Gerald Cheung

IPC分类号： H04L12/28

CPC分类号： H04L12/4633 ,  H04L12/66

摘要： A network device includes an interface and packet processing logic. The interface receives a multicast packet. The packet processing logic determines identifier data corresponding to the received multicast packet and replicates the identifier data to multiple outgoing packet forward engines at a first point in a processing path. The packet processing logic further replicates the identifier data to multiple data streams at a second point in the processing path and replicates the identifier data to multiple logical interfaces in the same stream at a third point in the processing path.

摘要翻译： 网络设备包括接口和分组处理逻辑。 接口收到组播报文。 分组处理逻辑确定与所接收的多播分组相对应的标识符数据，并且在处理路径的第一点将标识符数据复制到多个输出分组转发引擎。 分组处理逻辑还将标识符数据复制到处理路径中的第二点处的多个数据流，并且在处理路径中的第三点将标识符数据复制到同一流中的多个逻辑接口。

公开(公告)号：US20050086625A1

公开(公告)日：2005-04-21

申请号：US10973896

申请日：2004-10-27

申请人： Chong Lin ,  Tatao Chuang ,  Tran Long ,  Hy Hoang

发明人： Chong Lin ,  Tatao Chuang ,  Tran Long ,  Hy Hoang

IPC分类号： G06F17/50 ,  H01L23/528

CPC分类号： H01L23/5286 ,  G06F17/5068 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method for manufacturing a power bus on a chip, where the power bus has slits generated therein. The present invention relates to a method to manufacture a power bus in which the reference to a layout data base shows the coordinate location of the power buses in the chip. A height and width for the power bus is calculated based on its coordinates. Based on the height and width of the power buses and the predetermined size and spacing between power slits, a number of power slits to be generated is determined. These power slits are then generated by adding the power slits to the power bus in the coordinates of the layout database. The method of the present invention also generates power slits for use in manufacturing power buses on a chip for cases in which the power buses overlap.

摘要翻译： 一种在芯片上制造电力总线的方法，其中电源总线上产生狭缝。 本发明涉及一种制造电源总线的方法，其中对布线数据库的参考表示芯片中电源总线的坐标位置。 电源总线的高度和宽度根据其坐标进行计算。 基于电源总线的高度和宽度以及功率狭缝之间的预定尺寸和间隔，确定要产生的多个功率狭缝。 然后通过在布局数据库的坐标中将功率狭缝添加到电源总线来产生这些功率狭缝。 本发明的方法还产生用于在电源总线重叠的情况下制造芯片上的电源总线的电源插槽。

公开(公告)号：US07710994B1

公开(公告)日：2010-05-04

申请号：US11854001

申请日：2007-09-12

申请人： Pradeep Sindhu ,  Debashis Basu ,  Pankaj Patel ,  Raymond Lim ,  Avanindra Godbole ,  Tatao Chuang ,  Chi-Chung K. Chen ,  Jeffrey G. Libby ,  Dennis Fersuson ,  Philippe Lacroute ,  Gerald Cheung

发明人： Pradeep Sindhu ,  Debashis Basu ,  Pankaj Patel ,  Raymond Lim ,  Avanindra Godbole ,  Tatao Chuang ,  Chi-Chung K. Chen ,  Jeffrey G. Libby ,  Dennis Fersuson ,  Philippe Lacroute ,  Gerald Cheung

IPC分类号： H04J3/26

CPC分类号： H04L12/4633 ,  H04L12/66

摘要： A network device constructs a notification corresponding to a received multicast data unit, where the notification includes administrative data associated with the multicast data unit that does not include a payload of the multicast data unit. The network device replicates the notification at least three different processing elements at different locations in a processing path of the network device to produce multiple replicated data items and produces a copy of the multicast data unit for each of replicated notifications. The network device forwards each copy of the multicast data unit towards a multicast destination.

摘要翻译： 网络设备构建对应于所接收的多播数据单元的通知，其中通知包括与不包括多播数据单元的有效载荷的多播数据单元相关联的管理数据。 网络设备在网络设备的处理路径中的不同位置处至少复制三个不同的处理元件，以产生多个复制数据项，并为每个复制的通知产生多播数据单元的副本。 网络设备将组播数据单元的每个副本转发到组播目的地。

公开(公告)号：US07243184B1

公开(公告)日：2007-07-10

申请号：US10193212

申请日：2002-07-12

申请人： Dennis C. Ferguson ,  Philippe Lacroute ,  Chi-Chung Chen ,  Gerald Cheung ,  Tatao Chuang ,  Pankaj Patel ,  Visweh Ananthakrishnan

发明人： Dennis C. Ferguson ,  Philippe Lacroute ,  Chi-Chung Chen ,  Gerald Cheung ,  Tatao Chuang ,  Pankaj Patel ,  Visweh Ananthakrishnan

IPC分类号： G06F12/00 ,  H04L12/66 ,  H04L12/28

CPC分类号： H04L49/90 ,  H04L47/50 ,  H04L47/6225 ,  H04L49/3036 ,  H04L49/351 ,  H04L49/901 ,  H04L49/9094

摘要： Ordering logic ensures that data items being processed by a number of parallel processing units are unloaded from the processing units in the original per-flow order that the data items were loaded into the parallel processing units. The ordering logic includes a pointer memory, a tail vector, and a head vector. Through these three elements, the ordering logic keeps track of a number of “virtual queues” corresponding to the data flows. A round robin arbiter unloads data items from the processing units only when a data item is at the head of its virtual queue.

摘要翻译： 订购逻辑确保由多个并行处理单元处理的数据项以原始每流顺序从处理单元卸载，数据项被加载到并行处理单元中。 排序逻辑包括指针存储器，尾部矢量和头部矢量。 通过这三个元素，排序逻辑跟踪与数据流相对应的多个“虚拟队列”。 循环仲裁器只有在数据项位于其虚拟队列的头部时才从处理单元中卸载数据项。

公开(公告)号：US20060253826A1

公开(公告)日：2006-11-09

申请号：US11483638

申请日：2006-07-11

申请人： Chong Lin ,  Tatao Chuang ,  Tran Long ,  Hy Hoang

发明人： Chong Lin ,  Tatao Chuang ,  Tran Long ,  Hy Hoang

IPC分类号： G06F17/50

CPC分类号： H01L23/5286 ,  G06F17/5068 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method for manufacturing a power bus on a chip, where the power bus has slits generated therein. The present invention relates to a method to manufacture a power bus in which the reference to a layout data base shows the coordinate location of the power buses in the chip. A height and width for the power bus is calculated based on its coordinates. Based on the height and width of the power buses and the predetermined size and spacing between power slits, a number of power slits to be generated is determined. These power slits are then generated by adding the power slits to the power bus in the coordinates of the layout database. The method of the present invention also generates power slits for use in manufacturing power buses on a chip for cases in which the power buses overlap.