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    Systems and methods for monitoring integrated circuit internal states
    3.
    发明授权
    Systems and methods for monitoring integrated circuit internal states 失效
    监控集成电路内部状态的系统和方法

    公开(公告)号：US07009416B1

    公开(公告)日：2006-03-07

    申请号：US09984325

    申请日：2001-10-29

    申请人： Tatao Chuang ,  Devereaux C. Chen

    发明人： Tatao Chuang ,  Devereaux C. Chen

    IPC分类号： G01R31/02 ,  G01R31/26

    CPC分类号： G01R31/3177

    摘要： A system for monitoring internal states of an integrated circuit includes logic nodes, selection logic and a monitor unit. The logic nodes are disposed within the integrated circuit and the selection logic is coupled to monitor pins externally accessible on the integrated circuit. The selection logic retrieves internal states of select logic nodes based on signals applied via the monitor pins. The monitor unit reads the internal states of the select logic nodes via the monitor pins.

    摘要翻译： 用于监视集成电路的内部状态的系统包括逻辑节点，选择逻辑和监视器单元。 逻辑节点设置在集成电路内，并且选择逻辑耦合到集成电路上外部可访问的监视引脚。 选择逻辑基于通过监视器引脚施加的信号来检索选择逻辑节点的内部状态。 监视器单元通过监视器引脚读取选择逻辑节点的内部状态。

    Integrated circuit device having improved junction connections
    5.
    发明授权
    Integrated circuit device having improved junction connections 失效
    具有改进的结连接的集成电路装置

    公开(公告)号：US5121186A

    公开(公告)日：1992-06-09

    申请号：US601037

    申请日：1990-10-23

    申请人： Siu-Weng S. Wong ,  Devereaux C. Chen ,  Kuang-Yi Chiu

    发明人： Siu-Weng S. Wong ,  Devereaux C. Chen ,  Kuang-Yi Chiu

    IPC分类号： H01L21/28 ,  H01L21/336 ,  H01L21/768

    CPC分类号： H01L29/665 ,  H01L21/28 ,  H01L21/76889 ,  H01L21/76895 ,  H01L2924/0002

    摘要： A method for forming a contact to a selective region of an integrated circuit characterized by the steps of: forming a layer of refractory metal over and around the selected region; forming a layer of amorphous silicon over the layer of refractory metal; patterning the amorphous silicon in to an elongated strip which extends away from the selected region; annealing the integrated circuit to convert the strip of amorphous silicon into a silicide path; and removing the unreacted refractory metal. The method of the present invention can be used to extend a contact to the source, drain, or gate of a MOSFET from the top of an adjacent section of field oxide, and can also be used as a method for local interconnection of IC devices, such as CMOS devices.

    摘要翻译： 一种用于形成与集成电路的选择区域的接触的方法，其特征在于以下步骤：在所选择的区域上方和周围形成难熔金属层; 在难熔金属层上形成一层非晶硅; 将非晶硅图案化成延伸远离所选择的区域的细长条带; 对集成电路退火以将非晶硅带转变成硅化物路径; 并除去未反应的难熔金属。 本发明的方法可以用于从场氧化物的相邻部分的顶部延伸到MOSFET的源极，漏极或栅极的接触，并且还可以用作IC器件的局部互连的方法， 如CMOS器件。

    Systems and methods for re-ordering data in distributed data forwarding
    6.
    发明授权
    Systems and methods for re-ordering data in distributed data forwarding 有权
    在分布式数据转发中重新排序数据的系统和方法

    公开(公告)号：US08170028B1

    公开(公告)日：2012-05-01

    申请号：US12511856

    申请日：2009-07-29

    申请人： Dennis C Ferguson ,  Hann-Hwan Ju ,  Atsushi Kasuya ,  Gerald Cheung ,  Devereaux C Chen

    发明人： Dennis C Ferguson ,  Hann-Hwan Ju ,  Atsushi Kasuya ,  Gerald Cheung ,  Devereaux C Chen

    IPC分类号： H04L12/56

    CPC分类号： H04L69/14

    摘要： A network device includes an input interface, at least one processing path and an output interface. The input interface receives data units on a plurality of streams and assigns a first sequence number to each of the received data units. The at least one processing path performs a route look-up for each of the data units, where the route look-up determines a routing destination for a respective data unit. The output interface assigns a second sequence number to each of the processed data units based on a number of memory references associated with the route look-up for each of the data units and re-orders the processed data units based on the second sequence number assigned to each of the processed data units.

    摘要翻译： 网络设备包括输入接口，至少一个处理路径和输出接口。 输入接口在多个流上接收数据单元，并向每个接收到的数据单元分配第一序列号。 至少一个处理路径对每个数据单元执行路线查找，其中路线查找确定相应数据单元的路由目的地。 输出接口基于与每个数据单元的路由查找相关联的存储器引用的数量为每个处理的数据单元分配第二序列号，并且基于分配的第二序列号重新排序处理后的数据单元 到每个处理的数据单元。

    Low latency request dispatcher
    7.
    发明授权
    Low latency request dispatcher 有权
    低延迟请求调度程序

    公开(公告)号：US08001335B2

    公开(公告)日：2011-08-16

    申请号：US12878810

    申请日：2010-09-09

    申请人： Devereaux C. Chen ,  Jeffrey R. Zimmer

    发明人： Devereaux C. Chen ,  Jeffrey R. Zimmer

    IPC分类号： G06F12/00

    CPC分类号： G06F5/065 ,  G06F2207/3868

    摘要： A first-in-first-out (FIFO) queue optimized to reduce latency in dequeuing data items from the FIFO. In one implementation, a FIFO queue additionally includes buffers connected to the output of the FIFO queue and bypass logic. The buffers act as the final stages of the FIFO queue. The bypass logic causes input data items to bypass the FIFO and to go straight to the buffers when the buffers are able to receive data items and the FIFO queue is empty. In a second implementation, arbitration logic is coupled to the queue. The arbitration logic controls a multiplexer to output a predetermined number of data items from a number of final stages of the queue. In this second implementation, the arbitration logic gives higher priority to data items in later stages of the queue.

    摘要翻译： 优化先进先出（FIFO）队列，以减少从FIFO中出现数据项的延迟。 在一个实现中，FIFO队列还包括连接到FIFO队列和旁路逻辑的输出的缓冲器。 缓冲器作为FIFO队列的最后阶段。 当缓冲区能够接收数据项且FIFO队列为空时，旁路逻辑会使输入数据项绕过FIFO并直接进入缓冲区。 在第二实施例中，仲裁逻辑被耦合到队列。 仲裁逻辑控制多路复用器从队列的多个最后阶段输出预定数量的数据项。 在该第二实施方式中，仲裁逻辑给队列的较后阶段的数据项赋予更高的优先级。

    System, apparatus, and method for increasing resiliency in communications
    8.
    发明授权
    System, apparatus, and method for increasing resiliency in communications 有权
    提高通信弹性的系统，装置和方法

    公开(公告)号：US07986717B2

    公开(公告)日：2011-07-26

    申请号：US12492967

    申请日：2009-06-26

    申请人： Dennis C. Ferguson ,  Devereaux C. Chen ,  Eric M. Verwillow ,  Ramesh Padmanabhan ,  Thomas Michael Skibo

    发明人： Dennis C. Ferguson ,  Devereaux C. Chen ,  Eric M. Verwillow ,  Ramesh Padmanabhan ,  Thomas Michael Skibo

    IPC分类号： H04J3/06

    CPC分类号： H04J3/1617 ,  H04J2203/0082 ,  H04L2007/045

    摘要： A transmitting system inserts runt abort packets in an outgoing data stream during idle time inter-frame time fill. The runt abort packets cause the receiving system to synchronize itself to the transmitting system so that even if an error during inter-frame time fill causes the receiving system to go into an erroneous state, the receiving system will be synchronized with the transmitting system before receiving valid data. In one embodiment, the transmitting system transmits data in packets over SONET. The packet data is scrambled at the transmitting end and descrambled at the receiving end. Runt abort packets sent during inter-frame time fill resynchronize the descrambler. If there is an error in the inter-frame time fill bytes, causing the receiving end descrambler to no longer be synchronized with the transmitting end scrambler, the runt abort packets will cause the descrambler to resynchronize state with the transmitting scrambler.

    摘要翻译： 发送系统在空闲时间间隔间时间填充期间，将输出数据流中的中断中止分组插入。 中断中止分组使得接收系统使其自身与发射系统同步，使得即使在帧间时间填充期间的错误导致接收系统进入错误状态，接收系统将在接收之前与发射系统同步 有效数据。 在一个实施例中，发送系统通过SONET发送数据包。 分组数据在发送端进行加扰并在接收端进行解扰。 在跨帧时间填充期间发送的Runt中止包重新同步解扰器。 如果在帧间时间填充字节中存在错误，导致接收端解扰器不再与发送端加扰器同步，则中断中止分组将使解扰器与发送加扰器重新同步状态。

    LOW LATENCY REQUEST DISPATCHER
    9.
    发明申请
    LOW LATENCY REQUEST DISPATCHER 有权
    低期请求发放者

    公开(公告)号：US20110010474A1

    公开(公告)日：2011-01-13

    申请号：US12878810

    申请日：2010-09-09

    申请人： Devereaux C. CHEN ,  Jeffrey R. Zimmer

    发明人： Devereaux C. CHEN ,  Jeffrey R. Zimmer

    IPC分类号： G06F3/00 ,  G06F5/00

    CPC分类号： G06F5/065 ,  G06F2207/3868

    摘要： A first-in-first-out (FIFO) queue optimized to reduce latency in dequeuing data items from the FIFO. In one implementation, a FIFO queue additionally includes buffers connected to the output of the FIFO queue and bypass logic. The buffers act as the final stages of the FIFO queue. The bypass logic causes input data items to bypass the FIFO and to go straight to the buffers when the buffers are able to receive data items and the FIFO queue is empty. In a second implementation, arbitration logic is coupled to the queue. The arbitration logic controls a multiplexer to output a predetermined number of data items from a number of final stages of the queue. In this second implementation, the arbitration logic gives higher priority to data items in later stages of the queue.

    摘要翻译： 优化先进先出（FIFO）队列，以减少从FIFO中出现数据项的延迟。 在一个实现中，FIFO队列还包括连接到FIFO队列和旁路逻辑的输出的缓冲器。 缓冲器作为FIFO队列的最后阶段。 当缓冲区能够接收数据项且FIFO队列为空时，旁路逻辑会使输入数据项绕过FIFO并直接进入缓冲区。 在第二实施例中，仲裁逻辑被耦合到队列。 仲裁逻辑控制多路复用器从队列的多个最后阶段输出预定数量的数据项。 在该第二实施方式中，仲裁逻辑给队列的较后阶段的数据项赋予更高的优先级。

    HIGH PERFORMANCE PROBABILISTIC RATE POLICER
    10.
    发明申请
    HIGH PERFORMANCE PROBABILISTIC RATE POLICER 有权
    高性能概率速率策略器

    公开(公告)号：US20100177638A1

    公开(公告)日：2010-07-15

    申请号：US12732370

    申请日：2010-03-26

    申请人： Dennis C. Ferguson ,  Devereaux C. Chen ,  John W. Stewart, III ,  James Washburn ,  Jeffrey R. Zimmer

    发明人： Dennis C. Ferguson ,  Devereaux C. Chen ,  John W. Stewart, III ,  James Washburn ,  Jeffrey R. Zimmer

    IPC分类号： H04L12/56

    CPC分类号： H04L47/10 ,  H04L47/20 ,  H04L47/39

    摘要： A data flow rate policer enforces data flow policies for a number of data flows using a probabilistic policy enforcement mechanism. The policer includes a memory that stores the state of each data flow in a compact data structure. Additionally, the policer includes one or more policing engines that implement the actual data flow policies based on information derived from the data structures. The policing engines may be implemented in hardware to increase performance.

    摘要翻译： 数据流速策略器使用概率策略执行机制来执行多个数据流的数据流策略。 监管者包括一个存储器，它将每个数据流的状态存储在紧凑的数据结构中。 另外，监管者还包括一个或多个监管引擎，其基于从数据结构导出的信息来实现实际的数据流策略。 警务引擎可以以硬件实现以提高性能。