-
1.发明申请公开(公告)号：US20060291307A1
公开(公告)日：2006-12-28
申请号：US11260486
申请日：2005-10-28
IPC分类号： G11C29/00
CPC分类号： G11C29/06 , G11C29/10 , G11C2029/0405 , G11C2029/1204 , G11C2029/3602
摘要： A burn-in test, including first to sixth steps where voltages are applied for the same lengths of time in each step, is applied to a semiconductor memory having alternately arranged bit line pairs with twist structure where the bit lines cross each other and bit line pairs with non-twist structure where the bit lines are parallel to each other. Since lengths of time in which a stress is applied for all bit lines can be equally set, no deviation occurs in lengths of time where stress is applied between the bit lines. Characteristics of memory cells can be prevented from excessively deteriorating from the burn-in test. Further, the number of bit lines not having stress applied can be minimized in the first to sixth steps. Accordingly, the ratio of the bit lines having stress applied can be increased, which reduces the burn-in test time. Thus, test cost can be reduced.
摘要翻译： 包括在每个步骤中施加相同时间长度的电压的第一至第六步骤的老化测试被施加到具有交替排列的位线对的半导体存储器，其中位线彼此交叉并且位线 对，其中位线彼此平行的非扭转结构。 由于可以对所有位线施加应力的时间长度，所以在位线之间施加应力的时间长度不会发生偏差。 可以防止记忆单元的特性从老化测试过度恶化。 此外，在第一至第六步骤中可以使不具有应力的位线的数量最小化。 因此，可以增加施加了应力的位线的比例，这降低了老化测试时间。 因此，可以降低测试成本。
-
2.发明授权公开(公告)号：US07200059B2
公开(公告)日：2007-04-03
申请号：US11260486
申请日：2005-10-28
IPC分类号： G11C29/00
CPC分类号： G11C29/06 , G11C29/10 , G11C2029/0405 , G11C2029/1204 , G11C2029/3602
摘要： A burn-in test, including first to sixth steps where voltages are applied for the same lengths of time in each step, is applied to a semiconductor memory having alternately arranged bit line pairs with twist structure where the bit lines cross each other and bit line pairs with non-twist structure where the bit lines are parallel to each other. Since lengths of time in which a stress is applied for all bit lines can be equally set, no deviation occurs in lengths of time where stress is applied between the bit lines. Characteristics of memory cells can be prevented from excessively deteriorating from the burn-in test. Further, the number of bit lines not having stress applied can be minimized in the first to sixth steps. Accordingly, the ratio of the bit lines having stress applied can be increased, which reduces the burn-in test time. Thus, test cost can be reduced.
摘要翻译： 包括在每个步骤中施加相同时间长度的电压的第一至第六步骤的老化测试被施加到具有交替排列的位线对的半导体存储器，其中位线彼此交叉并且位线 对，其中位线彼此平行的非扭转结构。 由于可以对所有位线施加应力的时间长度，所以在位线之间施加应力的时间长度不会发生偏差。 可以防止记忆单元的特性从老化测试过度恶化。 此外，在第一至第六步骤中可以使不具有应力的位线的数量最小化。 因此，可以增加施加了应力的位线的比例，这降低了老化测试时间。 因此，可以降低测试成本。
-
公开(公告)号：US5258639A
公开(公告)日：1993-11-02
申请号：US971131
申请日：1992-11-04
申请人： Tatsuhiro Watanabe
发明人： Tatsuhiro Watanabe
IPC分类号： G11C11/401 , G11C11/4097 , H01L27/02 , H01L23/48 , H01L27/10 , H01L29/46
CPC分类号： G11C11/4097 , H01L2924/0002
摘要： A semiconductor memory device includes respective regions of a column decoder and a sense amplifier drive circuit arranged to lie opposite to each other on a semiconductor chip, respective regions of a memory cell array, a column gate and a sense amplifier arranged between the regions of the column decoder and the sense amplifier drive circuit, a plurality of column selection lines led out from the region of the column decoder, connected to respective column gate portions of the region of the column gate, and collected and arranged with units of groups of a predetermined number above the region of the column gate so as to have a smaller arrangement pitch than that of the column gate portion, and at least one sense amplifier drive signal line led out from the region of the sense amplifier drive circuit, connected to respective sense amplifier portions of the region of the sense amplifier, and arranged above the region of the sense amplifier so as to lie next to each group of the column selection lines. By the constitution, it is possible to constitute the memory device without any problem or difficulty from a viewpoint of the layout thereof even if it is a large capacity memory such as a 16 M-bit DRAM.
-
-
搜索结果
3 条记录 (耗时 0.009 秒)
