公开(公告)号：US5929521A

公开(公告)日：1999-07-27

申请号：US828255

申请日：1997-03-26

申请人： James M. Wark ,  Salman Akram

发明人： James M. Wark ,  Salman Akram

IPC分类号： H01L21/60 ,  H01L23/485 ,  H01L23/498 ,  H05K3/32 ,  H05K3/40 ,  H01L23/48 ,  H01L23/52 ,  H01L29/46

CPC分类号： H01L24/10 ,  G01R1/06738 ,  H01L22/34 ,  H01L23/49811 ,  H01L23/49816 ,  H01L24/13 ,  H01L24/81 ,  H05K3/325 ,  H05K3/4007 ,  H01L2224/0401 ,  H01L2224/05551 ,  H01L2224/05552 ,  H01L2224/05553 ,  H01L2224/05554 ,  H01L2224/05555 ,  H01L2224/13 ,  H01L2224/13099 ,  H01L2224/13111 ,  H01L2224/13144 ,  H01L2224/16 ,  H01L2224/1601 ,  H01L2224/81191 ,  H01L2224/81385 ,  H01L2224/81801 ,  H01L24/12 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01042 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01072 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01077 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01087 ,  H01L2924/014 ,  H01L2924/09701 ,  H01L2924/10253 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/15787 ,  H05K2201/0367 ,  H05K2201/0373 ,  H05K2201/10734 ,  Y10T29/49147 ,  Y10T29/49155

摘要： A bumped semiconductor device contact structure is disclosed including at least one non-planar contact pad having a plurality of projections extending therefrom for contacting at least one solder ball of a bumped integrated circuit (IC) device, such as a bumped die and a bumped packaged IC device. The projections are arranged to make electrical contact with the solder balls of a bumped IC device without substantially deforming the solder ball. Accordingly, reflow of solder balls to reform the solder balls is not necessary with the contact pad of the present invention. Such a contact pad may be provided on various testing equipment such as probes and the like and may be used for both temporary and permanent connections. Also disclosed is an improved method of forming the contact pads by etching and deposition.

摘要翻译： 公开了凸起的半导体器件接触结构，其包括至少一个非平面接触焊盘，其具有从其延伸的多个突起，用于接触凸起的集成电路（IC）器件的至少一个焊球，例如凸起的裸片和凸起的封装 IC设备。 突起被布置成与凸起的IC器件的焊球电接触，而不会使焊球基本上变形。 因此，本发明的接触焊盘不需要焊球的回流以重新形成焊球。 这样的接触垫可以设置在诸如探针等的各种测试设备上，并且可以用于临时和永久连接。 还公开了通过蚀刻和沉积形成接触焊盘的改进方法。

公开(公告)号：US5514910A

公开(公告)日：1996-05-07

申请号：US364226

申请日：1994-12-27

申请人： Kuniaki Koyama

发明人： Kuniaki Koyama

IPC分类号： H01L21/28 ,  H01L21/3205 ,  H01L21/74 ,  H01L21/768 ,  H01L23/485 ,  H01L23/52 ,  H01L23/522 ,  H01L29/46 ,  H01L29/54

CPC分类号： H01L23/485 ,  H01L21/743 ,  H01L2924/0002

摘要： A semiconductor device comprises a silicon via-plug within a fine via-hole in direct contact with an inner wall of the via-hole. A metal silicide layer is formed between an interconnection layer and the silicon plug as well as between the silicon plug and a diffused layer formed in a substrate. Shape defects and excessive stresses formed within a fine via-hole are reduced because the via-hole is filled with the silicon plug substantially without a metallic film or a metal silicide film on a sidewall. The metal silicide film is formed by a heat treatment through silicidation reaction.

摘要翻译： 半导体器件包括与通孔的内壁直接接触的细通孔内的硅通孔。 在互连层和硅插塞之间以及在硅插头和形成在衬底中的扩散层之间形成金属硅化物层。 由于通孔填充有基本上没有金属膜的硅插塞或侧壁上的金属硅化物膜，所以在细通孔内形成的形状缺陷和过大的应力减小。 金属硅化物膜通过硅化反应的热处理形成。

公开(公告)号：US5485035A

公开(公告)日：1996-01-16

申请号：US174430

申请日：1993-12-28

申请人： Yih-Shung Lin ,  Kuei-Wu Huang ,  Lun-Tseng Lu

发明人： Yih-Shung Lin ,  Kuei-Wu Huang ,  Lun-Tseng Lu

IPC分类号： H01L21/28 ,  H01L21/302 ,  H01L21/3065 ,  H01L21/3205 ,  H01L21/768 ,  H01L23/522 ,  H01L23/48 ,  H01L29/46 ,  H01L29/54 ,  H01L29/62

CPC分类号： H01L21/76819

摘要： A method for planarization of an integrated circuit. After a first conducting layer is deposited and patterned, a first insulating layer is deposited over the device. A planarizing layer is then deposited over the integrated circuit and etched back. Portions of the planarizing layer may remain in the lower topographical regions of the first insulating layer to planarize the surface of the device. A second insulating layer is then deposited over the integrated circuit, followed by a third insulating layer. A contact via is formed through the layers to expose a portion of the first conducting layer. A second conducting layer can now be deposited and patterned on the device to make electrical contact with the first conducting layer.

摘要翻译： 一种集成电路的平坦化方法。 在沉积和图案化第一导电层之后，在器件上沉积第一绝缘层。 然后将平坦化层沉积在集成电路上并被回蚀刻。 平坦化层的一部分可以保留在第一绝缘层的下部形貌区域中，以使器件的表面平坦化。 然后在集成电路上沉积第二绝缘层，随后沉积第三绝缘层。 通过这些层形成接触通孔以暴露第一导电层的一部分。 现在可以在器件上沉积和图案化第二导电层以与第一导电层电接触。

公开(公告)号：USRE35109E

公开(公告)日：1995-12-05

申请号：US1613

申请日：1993-01-07

申请人： Akihiro Kubota ,  Rikio Sugiura ,  Tsuyoshi Aoki ,  Michio Ono

发明人： Akihiro Kubota ,  Rikio Sugiura ,  Tsuyoshi Aoki ,  Michio Ono

IPC分类号： H01L23/48 ,  H01L21/56 ,  H01L21/60 ,  H01L23/31 ,  H01L23/495 ,  H01L23/50 ,  H01L29/46 ,  H01L29/62 ,  H01L29/64

CPC分类号： H01L23/49537 ,  H01L21/565 ,  H01L23/3107 ,  H01L23/3135 ,  H01L23/3157 ,  H01L23/495 ,  H01L23/49503 ,  H01L23/49589 ,  H01L2224/45014 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/4826 ,  H01L2224/49171 ,  H01L2224/49175 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L2924/00014 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/19041 ,  Y10S257/916

摘要： In a plastic molded semiconductor device in which inner leads overlap a semiconductor chip in a molded plastic body, the width of the chip may be close to the width of the plastic body without a decrease in the high resistance of the inner leads to the pull out thereof from the plastic body, and the layout of the inner leads may be unrestricted since the inner leads may occupy the region above the chip.

摘要翻译： 在内部引线与模制塑料体中的半导体芯片重叠的塑料模制半导体器件中，芯片的宽度可以接近塑料体的宽度，而不会使内部引线的高电阻降低到拉出 并且内引线的布局可以是不受限制的，因为内引线可能占据芯片上方的区域。

公开(公告)号：US5449955A

公开(公告)日：1995-09-12

申请号：US221731

申请日：1994-04-01

申请人： Richard P. Debiec ,  Michael D. Evans ,  Warren J. Pendergast

发明人： Richard P. Debiec ,  Michael D. Evans ,  Warren J. Pendergast

IPC分类号： H01R12/32 ,  H01L21/60 ,  H01L23/498 ,  H01L25/16 ,  H01R12/04 ,  H05K1/09 ,  H05K1/14 ,  H05K3/24 ,  H05K3/38 ,  H01L23/48 ,  H01L29/46 ,  H01L29/54 ,  H01L29/62

CPC分类号： H05K3/3452 ,  H01L23/49866 ,  H01L25/16 ,  H05K3/244 ,  H05K3/388 ,  H01L2924/0002 ,  H05K2203/0315

摘要： A multilayer composite interconnection for use in circuits including thin film elements and electrical interconnections includes a copper barrier layer interposed between a nickel layer and a gold layer of the interconnection. The copper layer is in a thickness sufficient to bar or at least to restrict diffusion of nickel through the gold layer under processing and operating conditions. The interconnection multilayer composite interconnection includes in an ascending order, titanium, palladium or palladium-titanium alloy, copper, nickel, copper barrier and gold layers.

摘要翻译： 用于包括薄膜元件和电互连的电路的多层复合互连包括介于镍层和互连金层之间的铜阻挡层。 铜层的厚度足以阻止或至少在加工和操作条件下限制镍通过金层的扩散。 互连多层复合互连以升序方式包括钛，钯或钯 - 钛合金，铜，镍，铜屏障和金层。

公开(公告)号：US5444288A

公开(公告)日：1995-08-22

申请号：US270091

申请日：1994-07-01

申请人： Eino Jacobs

发明人： Eino Jacobs

IPC分类号： H01L27/04 ,  H01L21/822 ,  H01L27/02 ,  H01L27/118 ,  H01L23/48 ,  H01L29/46

CPC分类号： H01L27/0218 ,  H01L27/11807

摘要： An important problem in large integrated circuits is constituted by noise superimposed on the supply. This noise is particularly caused by switching of switching elements such as flipflops, and by heavily loaded output stages. These elements cause current peaks which may give rise to comparatively great fluctuations in voltage. This problem is solved at least to a great extent in CMOS circuits with standard cells or with custom layout blocks by means of an additional decoupling capacitance in the form of an extra well in the routing channels. The decoupling capacitance may be positioned immediately adjacent the switching element, which is favorable for suppressing the supply noise. Since the routing channels are generally not used for providing circuit elements, the chip surface area is not or substantially not increased by this extra capacitance.

摘要翻译： 大型集成电路中的一个重要问题是由叠加在电源上的噪声构成。 这种噪声特别是由诸如触发器之类的开关元件的切换以及重负载的输出级引起。 这些元件引起电流峰值，这可能导致电压相对较大的波动。 这个问题至少在很大程度上解决了具有标准单元的CMOS电路，或者通过在路由通道中额外的形式的附加去耦电容来定制布局块。 去耦电容可以紧邻开关元件定位，这有利于抑制电源噪声。 由于路由通道通常不用于提供电路元件，因此该额外的电容不会或基本上不增加芯片表面积。

公开(公告)号：US5406122A

公开(公告)日：1995-04-11

申请号：US143797

申请日：1993-10-27

申请人： Wah-Sang Wong ,  William D. Gray ,  Cheng P. Wen

发明人： Wah-Sang Wong ,  William D. Gray ,  Cheng P. Wen

IPC分类号： H01L23/485 ,  H01L23/532 ,  H01L23/48 ,  H01L29/46

CPC分类号： H01L23/53252 ,  H01L23/53242 ,  H01L24/11 ,  H01L24/13 ,  H01L2224/11 ,  H01L2224/1147 ,  H01L2224/13 ,  H01L2224/13099 ,  H01L2924/00013 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/09701 ,  H01L2924/10329 ,  H01L2924/14 ,  H01L2924/1423 ,  H01L2924/15787 ,  H01L2924/19041

摘要： A gallium arsenide Monolithic-Microwave-Integrated-Circuit (MMIC) flip chip or other microelectronic circuit structure (10) includes a plated gold bridge (28) which serves as metal interconnect crossover between sites (24,-26) on a substrate (12). A first inorganic dielectric passivation layer (16), preferably of silicon dioxide, is formed under and supports the bridge (28). A second inorganic dielectric passivation layer (30), also preferably of silicon dioxide, is formed over and encapsulates the bridge (28) and the chip surface. A titanium/gold/titanium membrane (22) is formed under the bridge (28) to enable adhesion of the bridge (28) to the first passivation layer (16) and form plating contacts for the bridge (28). A contact bump post (38) is formed in a bump hole or via (32) which extends through the first and second passivation layers (16,30) to a bump contact site (34) on the substrate (12). Another titanium/gold/titanium membrane (40) is formed on the bump post (38) and the wall of the bump via (32) to provide a plating contact for a bump (42) which is plated on the membrane (40) inside the bump via (32) where the bump post (38) is located.

摘要翻译： 砷化镓单片微波集成电路（MMIC）倒装芯片或其他微电子电路结构（10）包括镀金金桥（28），其作为在基板（12）上的位置（24,26）之间的金属互连交叉 ）。 第一无机介电钝化层（16），优选二氧化硅，形成在桥下（28）并支撑桥（28）。 在桥（28）和芯片表面上形成第二无机介电钝化层（30），也优选二氧化硅。 在桥（28）下形成钛/金/钛膜（22），以使得桥（28）能够与第一钝化层（16）粘合并形成桥（28）的电镀接触。 触点凸点（38）形成在凸起孔中，或者通过（32）延伸穿过第一和第二钝化层（16,30）到基底（12）上的凸块接触部位（34）。 在凸点（38）和凸块通孔（32）的壁上形成另一个钛/金/钛膜（40），以提供用于凸块（42）的电镀接触，该电镀接触电镀在膜（40）内部 凸起柱（38）所在的凸块通孔（32）。

公开(公告)号：US5391921A

公开(公告)日：1995-02-21

申请号：US83322

申请日：1993-06-29

申请人： Osamu Kudoh ,  Kenji Okada ,  Hiroshi Shiba ,  Takuya Katoh

发明人： Osamu Kudoh ,  Kenji Okada ,  Hiroshi Shiba ,  Takuya Katoh

IPC分类号： H01L21/768 ,  H01L23/522 ,  H01L23/532 ,  H01L23/48 ,  H01L29/46 ,  H01L29/54 ,  H01L29/62

CPC分类号： H01L23/5329 ,  H01L21/76801 ,  H01L21/7682 ,  H01L23/5222 ,  H01L2924/0002

摘要： A semiconductor device that has a feature in the spatial relationship between the wiring in a multi-level wiring and the intermediate insulating films. In the lower part of the second and/or subsequent levels of wiring there exist intermediate insulating films that have a pattern which is the same as the pattern of the wiring. Because of this arrangement, the intermediate insulating film does not exist between the wiring on the same level. The first structure of the multi-level wiring has the intermediate insulating films formed in wall-like shape, with the lower end of the intermediate insulating films reaching an underlying insulating layer formed on the surface of the semiconductor substrate. The second structure of the multi-level wiring is a quasi air gap metallization structure. As a result of realization of such structures, in the semiconductor device according to the present invention, the parasitic capacitance due to the coupling capacitances between the wiring can be reduced compared with a semiconductor device that has a structure in which the spaces between the wiring are filled with the intermediate films.

摘要翻译： 具有多层配线中的布线与中间绝缘膜之间的空间关系特征的半导体装置。 在第二和/或随后的布线层的下部存在具有与布线图案相同的图案的中间绝缘膜。 由于这种布置，中间绝缘膜不存在于同一层的布线之间。 多层布线的第一结构具有形成为壁状形状的中间绝缘膜，中间绝缘膜的下端到达形成在半导体基板的表面上的下面的绝缘层。 多层布线的第二结构是准气隙金属化结构。 作为实现这种结构的结果，在本发明的半导体器件中，与具有这样的结构的半导体器件相比，能够减少由于布线之间的耦合电容引起的寄生电容， 填充中间膜。

公开(公告)号：US5384483A

公开(公告)日：1995-01-24

申请号：US843507

申请日：1992-02-28

申请人： Kuei-Wu Huang

发明人： Kuei-Wu Huang

IPC分类号： H01L21/28 ,  H01L21/302 ,  H01L21/3065 ,  H01L21/768 ,  H01L23/522 ,  H01L29/46 ,  H01L29/54 ,  H01L29/62

CPC分类号： H01L21/76802

摘要： A method for forming contact vias in a integrated circuit which do not have planarizing material nearby. After a first insulating layer is deposited over the integrated circuit, a planarizing layer is deposited over the first insulating layer. The planarizing layer is etched back and portions of the planarizing layer may remain in the lower topographical regions of the first insulating layer to planarize the surface of the integrated circuit. A first masking layer is then formed over the surface of the integrated circuit. The openings created in the first masking layer have a size which is greater than the size of the contact vias to be formed. The first insulating layer is partially etched into so that portions of the planarizing layer near the locations of the contact vias are removed. The first masking layer is then removed, and a second insulating layer is deposited over the integrated circuit. A second masking layer having openings which define the locations of the contact vias to be created is then formed over the second insulating layer. The size of the openings in the second masking layer are smaller than the size of the openings in the first masking layer. The contact vias are then formed through the first and second insulating layers.

摘要翻译： 一种在不具有平面化材料的集成电路中形成接触孔的方法。 在集成电路上沉积第一绝缘层之后，在第一绝缘层上沉积平坦化层。 平坦化层被回蚀刻，平坦化层的部分可以保留在第一绝缘层的下部形貌区域中，以使集成电路的表面平坦化。 然后在集成电路的表面上形成第一掩模层。 在第一掩模层中产生的开口的尺寸大于要形成的接触孔的尺寸。 部分地蚀刻第一绝缘层，使得在接触通孔的位置附近的平坦化层的部分被去除。 然后去除第一掩模层，并且在集成电路上沉积第二绝缘层。 然后在第二绝缘层上形成具有限定要产生的接触孔的位置的开口的第二掩蔽层。 第二掩模层中的开口的尺寸小于第一掩模层中的开口的尺寸。 然后通过第一绝缘层和第二绝缘层形成接触孔。

公开(公告)号：US5369220A

公开(公告)日：1994-11-29

申请号：US949474

申请日：1992-10-23

申请人： Keizo Harada ,  Takatoshi Takikawa ,  Takao Maeda ,  Shunsuke Ban ,  Shosaku Yamanaka

发明人： Keizo Harada ,  Takatoshi Takikawa ,  Takao Maeda ,  Shunsuke Ban ,  Shosaku Yamanaka

IPC分类号： H01L23/14 ,  H01L23/495 ,  H01L23/498 ,  H05K1/05 ,  H01L39/02 ,  H01L23/48 ,  H01L29/46 ,  H01L29/62

CPC分类号： H05K1/053 ,  H01L23/142 ,  H01L23/49517 ,  H01L23/49531 ,  H01L23/49866 ,  H01L24/49 ,  H01L2224/45015 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/4903 ,  H01L2224/49051 ,  H01L24/45 ,  H01L24/48 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01038 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01077 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01088 ,  H01L2924/01327 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19107 ,  H05K2201/0179 ,  H05K2201/0317

摘要： A wiring board has a wiring circuit which is reliable and which can be easily miniaturized, and used for the production of a highly integrated, lighter, thinner, shorter, smaller and low-cost semiconductor device. This wiring board can be sealed in a plastic package. The wiring board has a metal plate and a thin-film dielectric layer formed on the surface of the metal plate. A semiconductor device is mounted on the surface of the dielectric layer or the exposed surface of the metal plate. Film wirings are formed on the dielectric layer. Each film wiring is in the form of a laminate formed by laminating, by vapor phase deposition or by plating, a an aluminum conductive layer, an adhesive layer of chromium, titanium or a laminate thereof, a diffusion barrier layer of nickel, copper or a laminate thereof, and a corrosion-preventive and wire bonding layer of gold. Such wirings may alternatively be in the form of a laminate formed by laminating an adhesive layer of chromium, aluminum, titanium or a laminate comprising at least two of such materials, a copper conductive layer, and a gold layer, or in the form of a laminate formed by laminating an aluminum conductive layer, a barrier layer of nickel, and a gold layer. Since the film wirings can be miniaturized easily, the density of the wirings can be increased. Also, since the wirings are made of aluminum or copper, they are inexpensive.

摘要翻译： PCT No.PCT / JP92 / 00198 Sec。 371日期：1992年10月23日 102（e）日期1992年10月23日PCT提交1992年2月24日PCT公布。 公开号WO92 / 15117 日期：1992年9月3日。线路板具有可靠的并且可以容易地小型化的布线电路，并且用于生产高度集成，更轻，更薄，更短，更小和更低成本的半导体器件。 该接线板可以用塑料封装密封。 布线板具有形成在金属板表面上的金属板和薄膜电介质层。 半导体器件安装在电介质层的表面或金属板的暴露表面上。 在电介质层上形成膜布线。 每个薄膜布线是通过气相沉积或电镀层压铝，导电层，铬，钛或其层压体的粘合剂层，镍，铜或铜的扩散阻挡层而形成的层压体 层压板，以及金的防腐蚀和引线接合层。 这种布线也可以是通过层压铬，铝，钛或包含这些材料中的至少两种的层压体，铜导电层和金层，或者以 通过层叠铝导电层，镍的阻挡层和金层形成的层压体。 由于薄膜布线可以容易地小型化，所以可以提高布线的密度。 此外，由于布线由铝或铜制成，所以价格便宜。