公开(公告)号：US06348883B2

公开(公告)日：2002-02-19

申请号：US09791280

申请日：2001-02-21

申请人： Takenori Okada ,  Keisuke Tanaka ,  Teruhiko Ushio

发明人： Takenori Okada ,  Keisuke Tanaka ,  Teruhiko Ushio

IPC分类号： H03M700

CPC分类号： H03M7/46 ,  G11B20/1426 ,  G11B2020/1461

摘要： A method and apparatus are described which demodulate channel bits modulated by an arbitrary one of two modulation schemes, by making use of a consolidated reference table with a small address space. The method of the invention comprises the steps of: generating first output bits for representing patterns that correspond to patterns represented by first channel bits other than those patterns being unable to exist under first RLL constraints, the first output bits having a lesser number of bits than the first channel bits; and generating second output bits for representing patterns that correspond to patterns represented by second channel bits other than those patterns being unable to exist under second RLL constraints, the patterns represented by the second output bits being located at discontinuous areas of the patterns represented by the first output bits, the second output bits having a lesser number of bits than the second channel bits. The first and second output bits are used for designating an address of a demodulating reference table.

公开(公告)号：US06587294B1

公开(公告)日：2003-07-01

申请号：US09413011

申请日：1999-10-05

申请人： Teruhiko Ushio ,  Toshio Kanai

发明人： Teruhiko Ushio ,  Toshio Kanai

IPC分类号： G11B509

CPC分类号： G11B20/1866

摘要： Method and apparatus to correct an error of read-out data from a data storage medium, particularly a bit shift error, is described. The correction apparatus includes a gray bit detection circuit which flags bits with a phase shift exceeding a threshold and determines whether the previous or next bit cell has a smaller phase error. An RLL error detection circuit and a table containing valid bit combinations may be used in combination with the gray bit detector to correct errors on-the-fly without degrading performance. An advantage of the invention is that it allows correction of errors without regard to conventional ECC and its maximum number of errors.

摘要翻译： 描述了从数据存储介质校正读出数据的错误，特别是位移错误的方法和装置。 校正装置包括灰阶检测电路，其以相移超过阈值的位进行标识，并确定前一位或下一位单元是否具有较小的相位误差。 RLL错误检测电路和包含有效位组合的表可以与灰度位检测器组合使用，以便在不降低性能的情况下即时校正错误。 本发明的优点在于它允许校正错误，而不考虑常规ECC及其最大错误数量。

公开(公告)号：US06370098B2

公开(公告)日：2002-04-09

申请号：US09791174

申请日：2001-02-21

申请人： Takenori Okada ,  Keisuke Tanaka ,  Teruhiko Ushio

发明人： Takenori Okada ,  Keisuke Tanaka ,  Teruhiko Ushio

IPC分类号： G11B700

CPC分类号： H03M7/46 ,  G11B20/1426 ,  G11B2020/1461

摘要： A method and apparatus are described which demodulate channel bits modulated by an arbitrary one of two modulation schemes, by making use of a consolidated reference table with a small address space. The method of the invention comprises the steps of: generating first output bits for representing patterns that correspond to patterns represented by first channel bits other than those patterns being unable to exist under first RLL constraints, the first output bits having a lesser number of bits than the first channel bits; and generating second output bits for representing patterns that correspond to patterns represented by second channel bits other than those patterns being unable to exist under second RLL constraints, the patterns represented by the second output bits being located at discontinuous areas of the patterns represented by the first output bits, the second output bits having a lesser number of bits than the second channel bits. The first and second output bits are used for designating an address of a demodulating reference table.

摘要翻译： 描述了通过使用具有小的地址空间的统一的参考表来解调由两个调制方案中的任意一个调制的信道位的方法和装置。 本发明的方法包括以下步骤：产生第一输出比特，用于表示对应于第一信道比特以外的模式所代表的模式，除了在第一RLL约束下不能存在的那些模式，第一输出比特的比特数少于 第一个通道位; 以及产生第二输出位，用于表示对应于除了在第二RLL约束下不能存在的那些模式以外的第二通道位表示的模式的模式，由第二输出位表示的模式位于由第一RLL表示的模式的不连续区域 输出位，第二输出位具有比第二通道位少的位数。 第一和第二输出位用于指定解调参考表的地址。

公开(公告)号：US06421309B1

公开(公告)日：2002-07-16

申请号：US09388751

申请日：1999-09-02

申请人： Toshio Kanai ,  Teruhiko Ushio

发明人： Toshio Kanai ,  Teruhiko Ushio

IPC分类号： G11B700

CPC分类号： G11B27/36 ,  G11B20/14 ,  G11B20/1426 ,  G11B27/3027 ,  G11B27/34 ,  G11B2220/2545 ,  G11B2220/2562

摘要： A maximum mark length detector comprising a total value register for storing a total value Lsum of measured mark lengths; a measured value register for storing a measured value of a mark length; an arithmetic unit for computing the sum Lp of a current measured value Lk and a previously measured value PLk stored in the measured value register and subtracting a maximum value Lmax from the total value Lsum when the total value Lsum reaches the measured maximum value Lmax; a counter to count the number of times the subtraction is performed; and a comparator for completing the detection when a count value C of the counter reaches a predetermined value.

摘要翻译： 最大标记长度检测器，包括用于存储测量标记长度的总值Lsum的总值寄存器; 用于存储标记长度的测量值的测量值寄存器; 用于计算当前测量值Lk的和Lp和存储在测量值寄存器中的先前测量值PLk的算术单元，并且当总值Lsum达到测量的最大值Lmax时从总值Lsum中减去最大值Lmax; 计数执行减法次数的计数器; 以及当计数器的计数值C达到预定值时完成检测的比较器。

公开(公告)号：US06233213B1

公开(公告)日：2001-05-15

申请号：US09197484

申请日：1998-11-20

申请人： Takenori Okada ,  Keisuke Tanaka ,  Teruhiko Ushio

发明人： Takenori Okada ,  Keisuke Tanaka ,  Teruhiko Ushio

IPC分类号： G11B700

CPC分类号： H03M7/46 ,  G11B20/1426 ,  G11B2020/1461

摘要： A method and apparatus are described which demodulate channel bits modulated by an arbitrary one of two modulation schemes, by making use of a consolidated reference table with a small address space. The method of the invention comprises the steps of: generating first output bits for representing patterns that correspond to patterns represented by first channel bits other than those patterns being unable to exist under first RLL constraints, the first output bits having a lesser number of bits than the first channel bits; and generating second output bits for representing patterns that correspond to patterns represented by second channel bits other than those patterns being unable to exist under second RLL constraints, the patterns represented by the second output bits being located at discontinuous areas of the patterns represented by the first output bits, the second output bits having a lesser number of bits than the second channel bits. The first and second output bits are used for designating an address of a demodulating reference table.

摘要翻译： 描述了通过使用具有小的地址空间的统一的参考表来解调由两个调制方案中的任意一个调制的信道位的方法和装置。 本发明的方法包括以下步骤：产生第一输出比特，用于表示对应于第一信道比特以外的模式所代表的模式，除了在第一RLL约束下不能存在的那些模式，第一输出比特的比特数少于 第一个通道位; 以及产生第二输出位，用于表示对应于除了在第二RLL约束下不能存在的那些模式以外的第二通道位表示的模式的模式，由第二输出位表示的模式位于由第一RLL表示的模式的不连续区域 输出位，第二输出位具有比第二通道位少的位数。 第一和第二输出位用于指定解调参考表的地址。

公开(公告)号：US06392566B2

公开(公告)日：2002-05-21

申请号：US09773225

申请日：2001-01-30

申请人： Teruhiko Ushio

发明人： Teruhiko Ushio

IPC分类号： H03M700

CPC分类号： G11B20/1426 ,  G11B20/18 ,  H03M5/145 ,  H03M13/31

摘要： A method and apparatus are provided for modulating code for use with written optical disks such as digital video disks (DVD). The invention falitates 8/16 modulation by eliminating duplicate code conversion and by reducing the number of times that conversion codes must be looked up from a conversion table. A conversion code corresponding to a received input code is specified from among a plurality of conversion codes. Duplication information corresponding to the input code is read from a pre-processing table and duplicate information indicated duplicate conversion codes in the plurality of conversion codes is stored. Conversion code corresponding to the input code is read from the conversion table and is selectively stored with duplicate conversion codes being omitted.

摘要翻译： 提供了一种方法和装置，用于调制用于诸如数字视盘（DVD）的书写光盘的代码。 本发明通过消除重复的代码转换和减少从转换表中查找转换代码的次数来改变8/16调制。 从多个转换代码中指定与接收的输入代码相对应的转换代码。 从预处理表读取与输入代码相对应的复制信息，并且存储指示多个转换代码中的重复转换代码的重复信息。 从转换表读取与输入代码相对应的转换代码，并且被选择性地存储，省略重复的转换代码。