Process for diffusing impurities into a semiconductor body vapor phase
diffusion of III-V semiconductor substrates
    1.
    发明授权
    Process for diffusing impurities into a semiconductor body vapor phase diffusion of III-V semiconductor substrates 失效
    将杂质扩散到III-V半导体衬底的半导体体气相扩散中的工艺

    公开(公告)号:US4592793A

    公开(公告)日:1986-06-03

    申请号:US712300

    申请日:1985-03-15

    摘要: A process for diffusing a dopant into a III-V type semiconductor body is disclosed which comprises:(a) placing in a heating chamber which is substantially devoid of any oxidizing substance a deposition substrate possessing a dopant-containing layer which has been vapor deposited upon a major surface thereof in contact with, or in the proximity of, an object substrate fabricated from a III-V type semiconductor material with the dopant-containing layer of the deposition substrate being substantially opposed to a major surface of the object substrate;(b) introducing into the heating chamber a source of Group V element corresponding to the Group V element of the object substrate, said source being capable of providing Group V element in the vapor phase at the diffusion temperature with the vapor pressure of the vapor phase Group V element being at or above the equilibrium vapor pressure of the Group V element present at the surface of the object substrate; and,(c) heating the deposition substrate and the object substrate to the diffusion temperature for a period of time sufficient to diffuse a predetermined amount of dopant into the object substrate to a predetermined depth therein.

    摘要翻译: 公开了一种将掺杂剂扩散到III-V型半导体本体中的方法,其包括:(a)放置在基本上没有任何氧化物质的加热室中,该沉积基底具有已经气相沉积的掺杂剂层 其主表面与由III-V型半导体材料制成的对象衬底接触或接近,其中沉积衬底的含掺杂剂层基本上与对象衬底的主表面相对; (b)将与对象基板的V族元素相对应的V族元素的源引入加热室,所述源能够在气相中以蒸气相的蒸气压提供气相中的V族元素 V族元素处于或高于存在于物体基板表面的V族元素的平衡蒸气压; 以及(c)将沉积基板和对象基板加热至扩散温度一段足以将预定量的掺杂剂扩散到目标基板中的时间段到其预定的深度。

    Single and double-gate pseudo-FET devices for semiconductor materials evaluation
    2.
    发明授权
    Single and double-gate pseudo-FET devices for semiconductor materials evaluation 失效
    用于半导体材料评估的单栅极和双栅极伪FET器件

    公开(公告)号:US07682846B2

    公开(公告)日:2010-03-23

    申请号:US12169190

    申请日:2008-07-08

    IPC分类号: H01L21/36

    摘要: Several methods and structures are disclosed for determining electrical properties of silicon-on-insulator (SOI) wafers and alternate versions of such wafers such as strained silicon:silicon/germanium:-on-insulator (SSGOI) wafers. The analyzed electrical properties include mobilities, interface state densities, and oxide charge by depositing electrodes on the wafer surface and measuring the current-voltage behavior using these electrodes. In a single gate structure, the source and drain electrodes reside on the wafer surface and the buried insulator acts as the gate oxide, with the substrate acting as the gate electrode. In a double gate structure, an oxide is used on the upper surface between the source and drain electrodes and an additional metal layer is used on top of this oxide to act as a second gate electrode. Light of broad spectrum or specific wavelength may be used to alter electrical carrier densities in the region between the electrodes to further analyze the electrical properties of the material, or alternatively, the device can be used as a detector of light having a wavelength shorter than the bandgap wavelength of the Si surface.

    摘要翻译: 公开了几种方法和结构,用于确定绝缘体上硅(SOI)晶片的电性能以及诸如应变硅:硅/锗:绝缘体(SSGOI)晶片之类的晶片的替代形式。 通过在晶片表面上沉积电极并测量使用这些电极的电流 - 电压行为,所分析的电特性包括迁移率,界面态密度和氧化物电荷。 在单个栅极结构中,源极和漏极位于晶片表面上,埋入的绝缘体用作栅极氧化物,衬底用作栅电极。 在双栅极结构中,在源极和漏极之间的上表面上使用氧化物,并且在该氧化物的顶部上使用附加的金属层作为第二栅电极。 可以使用宽光谱或特定波长的光来改变电极之间的区域中的电载体密度,以进一步分析材料的电学性质,或者替代地,该器件可以用作波长短于 Si表面的带隙波长。

    Single and double-gate pseudo-FET devices for semiconductor materials evaluation
    3.
    发明授权
    Single and double-gate pseudo-FET devices for semiconductor materials evaluation 失效
    用于半导体材料评估的单栅极和双栅极伪FET器件

    公开(公告)号:US07288446B2

    公开(公告)日:2007-10-30

    申请号:US11219919

    申请日:2005-09-06

    IPC分类号: H01L21/00 H01L21/84

    摘要: Several methods and structures are disclosed for determining electrical properties of silicon-on-insulator (SOI) wafers and alternate versions of such wafers such as strained silicon:silicon/germanium:-on-insulator (SSGOI) wafers. The analyzed electrical properties include mobilities, interface state densities, and oxide charge by depositing electrodes on the wafer surface and measuring the current-voltage behavior using these electrodes, In a single gate structure, the source and drain electrodes reside on the wafer surface and the buried insulator acts as the gate oxide, with the substrate acting as the gate electrode. In a double gate structure, an oxide is used on the upper surface between the source and drain electrodes and an additional metal layer is used on top of this oxide to act as a second gate electrode. Light of broad spectrum or specific wavelength may be used to alter electrical carrier densities in the region between the electrodes to further analyze the electrical properties of the material, or alternatively, the device can be used as a detector of light having a wavelength shorter than the bandgap wavelength of the Si surface.

    摘要翻译: 公开了几种方法和结构,用于确定绝缘体上硅(SOI)晶片的电性能以及诸如应变硅:硅/锗:绝缘体(SSGOI)晶片之类的晶片的替代形式。 分析的电气特性包括迁移率,界面态密度和通过在晶片表面上沉积电极并测量使用这些电极的电流 - 电压行为的氧化物电荷。在单个栅极结构中,源极和漏极驻留在晶片表面上,并且 掩埋绝缘体用作栅极氧化物,其中衬底用作栅电极。 在双栅极结构中,在源极和漏极之间的上表面上使用氧化物,并且在该氧化物的顶部上使用附加的金属层作为第二栅电极。 可以使用宽光谱或特定波长的光来改变电极之间的区域中的电载体密度,以进一步分析材料的电学性质,或者替代地,该器件可以用作波长短于 Si表面的带隙波长。

    Single and double-gate pseudo-FET devices for semiconductor materials evaluation
    4.
    发明授权
    Single and double-gate pseudo-FET devices for semiconductor materials evaluation 失效
    用于半导体材料评估的单栅极和双栅极伪FET器件

    公开(公告)号:US06955932B2

    公开(公告)日:2005-10-18

    申请号:US10696632

    申请日:2003-10-29

    摘要: Several methods and structures are disclosed for determining electrical properties of silicon-on-insulator (SOI) wafers and alternate versions of such wafers such as strained silicon:silicon/germanium:-on-insulator (SSGOI) wafers. The analyzed electrical properties include mobilities, interface state densities, and oxide charge by depositing electrodes on the wafer surface and measuring the current-voltage behavior using these electrodes. In a single gate structure, the source and drain electrodes reside on the wafer surface and the buried insulator acts as the gate oxide, with the substrate acting as the gate electrode. In a double gate structure, an oxide is used on the upper surface between the source and drain electrodes and an additional metal layer is used on top of this oxide to act as a second gate electrode. Light of broad spectrum or specific wavelength may be used to alter electrical carrier densities in the region between the electrodes to further analyze the electrical properties of the material, or alternatively, the device can be used as a detector of light having a wavelength shorter than the bandgap wavelength of the Si surface.

    摘要翻译: 公开了几种方法和结构,用于确定绝缘体上硅(SOI)晶片的电性能以及诸如应变硅:硅/锗:绝缘体(SSGOI)晶片之类的晶片的替代形式。 通过在晶片表面上沉积电极并测量使用这些电极的电流 - 电压行为,所分析的电特性包括迁移率,界面态密度和氧化物电荷。 在单个栅极结构中,源极和漏极位于晶片表面上,埋入的绝缘体用作栅极氧化物,衬底用作栅电极。 在双栅极结构中,在源极和漏极之间的上表面上使用氧化物,并且在该氧化物的顶部上使用附加的金属层作为第二栅电极。 可以使用宽光谱或特定波长的光来改变电极之间的区域中的电载体密度,以进一步分析材料的电学性质,或者替代地,该器件可以用作波长短于 Si表面的带隙波长。

    SINGLE AND DOUBLE-GATE PSEUDO-FET DEVICES FOR SEMICONDUCTOR MATERIALS EVALUATION
    5.
    发明申请
    SINGLE AND DOUBLE-GATE PSEUDO-FET DEVICES FOR SEMICONDUCTOR MATERIALS EVALUATION 失效
    用于半导体材料评估的单和双栅极PS器件

    公开(公告)号:US20080283919A1

    公开(公告)日:2008-11-20

    申请号:US12169190

    申请日:2008-07-08

    IPC分类号: H01L27/01 H01L21/00

    摘要: Several methods and structures are disclosed for determining electrical properties of silicon-on-insulator (SOI) wafers and alternate versions of such wafers such as strained silicon:silicon/germanium:-on-insulator (SSGOI) wafers. The analyzed electrical properties include mobilities, interface state densities, and oxide charge by depositing electrodes on the wafer surface and measuring the current-voltage behavior using these electrodes. In a single gate structure, the source and drain electrodes reside on the wafer surface and the buried insulator acts as the gate oxide, with the substrate acting as the gate electrode. In a double gate structure, an oxide is used on the upper surface between the source and drain electrodes and an additional metal layer is used on top of this oxide to act as a second gate electrode. Light of broad spectrum or specific wavelength may be used to alter electrical carrier densities in the region between the electrodes to further analyze the electrical properties of the material, or alternatively, the device can be used as a detector of light having a wavelength shorter than the bandgap wavelength of the Si surface.

    摘要翻译: 公开了几种方法和结构,用于确定绝缘体上硅(SOI)晶片的电性能以及诸如应变硅:硅/锗:绝缘体(SSGOI)晶片之类的晶片的替代形式。 通过在晶片表面上沉积电极并测量使用这些电极的电流 - 电压行为,所分析的电特性包括迁移率,界面态密度和氧化物电荷。 在单个栅极结构中,源极和漏极位于晶片表面上,埋入的绝缘体用作栅极氧化物,衬底用作栅电极。 在双栅极结构中,在源极和漏极之间的上表面上使用氧化物,并且在该氧化物的顶部上使用附加的金属层作为第二栅电极。 可以使用宽光谱或特定波长的光来改变电极之间的区域中的电载体密度,以进一步分析材料的电学性质,或者替代地,该器件可用作波长短于 Si表面的带隙波长。