公开(公告)号：US07643233B2

公开(公告)日：2010-01-05

申请号：US12110321

申请日：2008-04-27

Applicant: William Gene Bliss ,  Thomas V. Souvignier

Inventor： William Gene Bliss ,  Thomas V. Souvignier

IPC: G11B5/02

CPC classification number: G11B5/09 ,  G11B20/10009 ,  G11B20/10046 ,  G11B20/10222 ,  G11B20/10425 ,  G11B2220/2516

Abstract: A system reads data from a magnetic storage media. A read head reads data from the magnetic storage media and produce an analog signal. A variable gain amplifier amplifies the analog signal. An offset adjust module substantially centers the amplified analog signal to a midscale. A Magneto Resistive Asymmetry (MRA) collection module MRA corrects the amplified analog signal. A Continuous Time Filter (CTF) compensation module processes the amplified analog signal. An Analog to Digital Converter (ADC) samples the amplified analog signal based upon a control signal to produce a digital signal. A Disk Lock Clock (DLC) system produces the control signal to the ADC. The control signal is representative of a frequency offset caused by at least one servo wedge rate error. A Finite Impulse Response (FIR) filter module filters the digital signal. A sequence detector processes the digital signal and detects a bit sequence from the digital signal.

Abstract translation: 系统从磁存储介质读取数据。 读头从磁存储介质读取数据并产生模拟信号。 可变增益放大器放大模拟信号。 偏移调整模块将放大的模拟信号基本上居中， 磁阻非对称（MRA）采集模块MRA校正放大的模拟信号。 连续时间滤波器（CTF）补偿模块处理放大的模拟信号。 模数转换器（ADC）根据控制信号对放大的模拟信号进行采样以产生数字信号。 磁盘锁定时钟（DLC）系统产生到ADC的控制信号。 控制信号表示由至少一个伺服楔速率误差引起的频率偏移。 有限脉冲响应（FIR）滤波器模块对数字信号进行滤波。 序列检测器处理数字信号并从数字信号中检测位序列。

公开(公告)号：US08069397B2

公开(公告)日：2011-11-29

申请号：US11643067

申请日：2006-12-21

Applicant: Andrei E. Vityaev ,  Thomas V. Souvignier ,  Gregory L. Silvus

Inventor： Andrei E. Vityaev ,  Thomas V. Souvignier ,  Gregory L. Silvus

IPC: H03M13/00

CPC classification number: G11B20/10009 ,  G11B20/10296 ,  G11B20/1833 ,  G11B2220/2516 ,  H03M13/1102 ,  H03M13/3738

Abstract: A scheme in which a first decoder provides first decoding of a signal read from a disk. A second decoder, coupled to an output of the first decoder, combines with the first decoder to provide iterative decoding to recover data stored on the disk when in an iterative mode of operation. However, when in a non-iterative mode of operation, the output of the first decoder is coupled to an error correction code module to apply error correction code (ECC) to the output of the first decoder to recover data stored on the disk by non-iterative decoding.

Abstract translation: 一种方案，其中第一解码器提供从盘读取的信号的第一解码。 耦合到第一解码器的输出的第二解码器与第一解码器组合以提供迭代解码以在迭代操作模式下恢复存储在盘上的数据。 然而，当处于非迭代操作模式时，第一解码器的输出耦合到纠错码模块，以将错误校正码（ECC）应用于第一解码器的输出，以通过非恢复模式恢复存储在盘上的数据 - 解码。

公开(公告)号：US08024637B2

公开(公告)日：2011-09-20

申请号：US11855838

申请日：2007-09-14

Applicant: William Gene Bliss ,  Gregory L. Silvus ,  John P. Mead ,  Thomas V. Souvignier

Inventor： William Gene Bliss ,  Gregory L. Silvus ,  John P. Mead ,  Thomas V. Souvignier

IPC: H03M13/00

CPC classification number: H03M13/2966 ,  H03M13/1102 ,  H03M13/15 ,  H03M13/1515 ,  H03M13/258 ,  H03M13/2906 ,  H03M13/2909 ,  H03M13/2942 ,  H03M13/2957

Abstract: Super block error correction code (ECC) adaptable to communication systems including hard disk drives (HDDs) and other memory storage devices. A means is presented by which a number of blocks of information can be organized, with a degree of ECC provided thereto, and transmitted via a signal into a communication channel. In some instances, the communication channel is coupled to a storage media as in the context of an HDD, and information is written to and read from the storage media via this communication channel (e.g., “read channel”). This means is particularly well suited to applications that provide large amounts of data via any one transmission (e.g., DVR/PVR (Digital/Personal Video Recorder)). A redundant block is generated using the information of each of a number of information blocks thereby provided extra ECC on a large portion of data, and that redundant block also undergoes ECC encoding.

Abstract translation: 适用于包括硬盘驱动器（HDD）和其他存储器存储设备在内的通信系统的超块纠错码（ECC）。 提供了一种可以组织多个信息块的装置，其中提供了一定程度的ECC，并经由信号发送到通信信道中。 在一些情况下，通信信道如HDD的上下文中的那样被耦合到存储介质上，并且经由该通信信道（例如，“读取通道”）将信息写入存储介质并从存储介质读取信息。 这意味着特别适用于通过任何一种传输（例如，DVR / PVR（数字/个人录像机））提供大量数据的应用。 使用多个信息块中的每一个的信息生成冗余块，从而在大部分数据上提供额外的ECC，并且该冗余块也经历ECC编码。

公开(公告)号：US20080007855A1

公开(公告)日：2008-01-10

申请号：US11643172

申请日：2006-12-21

Applicant: Andrei E. Vityaev ,  Thomas V. Souvignier ,  Gregory L. Silvus

Inventor： Andrei E. Vityaev ,  Thomas V. Souvignier ,  Gregory L. Silvus

IPC: G11B5/09

CPC classification number: G11B5/09 ,  G11B20/10037 ,  G11B20/1403 ,  G11B2020/1836 ,  G11B2220/2516 ,  H03L7/0807

Abstract: A technique to sample a signal from a disk by using frequency and phase offset adjustment in a phase locked loop (PLL) timing recovery loop to sample read data from the disk, prior to a disk clocked clocking acquires a lock. Subsequently, sampling a signal from a disk by using only phase offset adjustment in the PLL timing recovery loop to sample read data from the disk after the disk clocked clocking acquires the lock. The sampled data is then error corrected by applying an error correction code (ECC).

Abstract translation: 通过使用锁相环（PLL）定时恢复循环中的频率和相位偏移调整来对来自磁盘的信号进行采样的技术，以在磁盘定时时钟获取锁之前对来自磁盘的读取数据进行采样。 随后，通过在PLL定时恢复循环中仅使用相位偏移调整从盘读取信号，以便在磁盘定时计时获取锁之后从盘读取数据。 然后通过应用纠错码（ECC）对采样数据进行纠错。

公开(公告)号：US08132084B2

公开(公告)日：2012-03-06

申请号：US13191628

申请日：2011-07-27

Applicant: William Gene Bliss ,  Gregory L. Silvus ,  John P. Mead ,  Thomas V. Souvignier

Inventor： William Gene Bliss ,  Gregory L. Silvus ,  John P. Mead ,  Thomas V. Souvignier

IPC: H03M13/00

CPC classification number: H03M13/2966 ,  H03M13/1102 ,  H03M13/15 ,  H03M13/1515 ,  H03M13/258 ,  H03M13/2906 ,  H03M13/2909 ,  H03M13/2942 ,  H03M13/2957

Abstract: Super block error correction code (ECC) adaptable to communication systems including hard disk drives (HDDs) and other memory storage devices. A means is presented by which a number of blocks of information can be organized, with a degree of ECC provided thereto, and transmitted via a signal into a communication channel. In some instances, the communication channel is coupled to a storage media as in the context of an HDD, and information is written to and read from the storage media via this communication channel (e.g., “read channel”). This means is particularly well suited to applications that provide large amounts of data via any one transmission (e.g., DVR/PVR (Digital/Personal Video Recorder)). A redundant block is generated using the information of each of a number of information blocks thereby provided extra ECC on a large portion of data, and that redundant block also undergoes ECC encoding.

Abstract translation: 适用于包括硬盘驱动器（HDD）和其他存储器存储设备在内的通信系统的超块纠错码（ECC）。 提供了一种可以组织多个信息块的装置，其中提供了一定程度的ECC，并经由信号发送到通信信道中。 在一些情况下，通信信道如HDD的上下文中的那样被耦合到存储介质上，并且经由该通信信道（例如，“读取通道”）将信息写入存储介质并从存储介质读取信息。 这意味着特别适用于通过任何一种传输（例如，DVR / PVR（数字/个人录像机））提供大量数据的应用。 使用多个信息块中的每一个的信息生成冗余块，从而在大部分数据上提供额外的ECC，并且该冗余块也经历ECC编码。

公开(公告)号：US20080266694A1

公开(公告)日：2008-10-30

申请号：US12110321

申请日：2008-04-27

Applicant: WILLIAM GENE BLISS ,  THOMAS V. SOUVIGNIER

Inventor： WILLIAM GENE BLISS ,  THOMAS V. SOUVIGNIER

IPC: G11B5/09

CPC classification number: G11B5/09 ,  G11B20/10009 ,  G11B20/10046 ,  G11B20/10222 ,  G11B20/10425 ,  G11B2220/2516

Abstract: A system reads data from a magnetic storage media. A read head reads data from the magnetic storage media and produce an analog signal. A variable gain amplifier amplifies the analog signal. An offset adjust module substantially centers the amplified analog signal to a midscale. A Magneto Resistive Asymmetry (MRA) collection module MRA corrects the amplified analog signal. A Continuous Time Filter (CTF) compensation module processes the amplified analog signal. An Analog to Digital Converter (ADC) samples the amplified analog signal based upon a control signal to produce a digital signal. A Disk Lock Clock (DLC) system produces the control signal to the ADC. The control signal is representative of a frequency offset caused by at least one servo wedge rate error. A Finite Impulse Response (FIR) filter module filters the digital signal. A sequence detector processes the digital signal and detects a bit sequence from the digital signal.

Abstract translation: 系统从磁存储介质读取数据。 读头从磁存储介质读取数据并产生模拟信号。 可变增益放大器放大模拟信号。 偏移调整模块将放大的模拟信号基本上居中， 磁阻非对称（MRA）采集模块MRA校正放大的模拟信号。 连续时间滤波器（CTF）补偿模块处理放大的模拟信号。 模数转换器（ADC）根据控制信号对放大的模拟信号进行采样以产生数字信号。 磁盘锁定时钟（DLC）系统产生到ADC的控制信号。 控制信号表示由至少一个伺服楔速率误差引起的频率偏移。 有限脉冲响应（FIR）滤波器模块对数字信号进行滤波。 序列检测器处理数字信号并从数字信号中检测位序列。

公开(公告)号：US20080022189A1

公开(公告)日：2008-01-24

申请号：US11643067

申请日：2006-12-21

Applicant: Andrei E. Vityaev ,  Thomas V. Souvignier ,  Gregory L. Silvus

Inventor： Andrei E. Vityaev ,  Thomas V. Souvignier ,  Gregory L. Silvus

IPC: G11C29/00

CPC classification number: G11B20/10009 ,  G11B20/10296 ,  G11B20/1833 ,  G11B2220/2516 ,  H03M13/1102 ,  H03M13/3738

Abstract: A scheme in which a first decoder provides first decoding of a signal read from a disk. A second decoder, coupled to an output of the first decoder, combines with the first decoder to provide iterative decoding to recover data stored on the disk when in an iterative mode of operation. However, when in a non-iterative mode of operation, the output of the first decoder is coupled to an error correction code module to apply error correction code (ECC) to the output of the first decoder to recover data stored on the disk by non-iterative decoding.

Abstract translation: 一种方案，其中第一解码器提供从盘读取的信号的第一解码。 耦合到第一解码器的输出的第二解码器与第一解码器组合以提供迭代解码以在迭代操作模式下恢复存储在盘上的数据。 然而，当处于非迭代操作模式时，第一解码器的输出耦合到纠错码模块，以将错误校正码（ECC）应用于第一解码器的输出，以通过非恢复模式恢复存储在盘上的数据 - 解码。

公开(公告)号：US20110283167A1

公开(公告)日：2011-11-17

申请号：US13191628

申请日：2011-07-27

Applicant: William Gene Bliss ,  Gregory L. Silvus ,  John P. Mead ,  Thomas V. Souvignier

Inventor： William Gene Bliss ,  Gregory L. Silvus ,  John P. Mead ,  Thomas V. Souvignier

IPC: H03M13/05 ,  G06F11/10

CPC classification number: H03M13/2966 ,  H03M13/1102 ,  H03M13/15 ,  H03M13/1515 ,  H03M13/258 ,  H03M13/2906 ,  H03M13/2909 ,  H03M13/2942 ,  H03M13/2957

Abstract: Super block error correction code (ECC) adaptable to communication systems including hard disk drives (HDDs) and other memory storage devices. A means is presented by which a number of blocks of information can be organized, with a degree of ECC provided thereto, and transmitted via a signal into a communication channel. In some instances, the communication channel is coupled to a storage media as in the context of an HDD, and information is written to and read from the storage media via this communication channel (e.g., “read channel”). This means is particularly well suited to applications that provide large amounts of data via any one transmission (e.g., DVR/PVR (Digital/Personal Video Recorder)). A redundant block is generated using the information of each of a number of information blocks thereby provided extra ECC on a large portion of data, and that redundant block also undergoes ECC encoding.

公开(公告)号：US07974035B2

公开(公告)日：2011-07-05

申请号：US11823612

申请日：2007-06-28

Applicant: William Gene Bliss ,  Thomas V. Souvignier ,  Andrei E. Vityaev ,  Gregory L. Silvus

Inventor： William Gene Bliss ,  Thomas V. Souvignier ,  Andrei E. Vityaev ,  Gregory L. Silvus

IPC: G11B5/09

CPC classification number: G11B5/09 ,  G11B27/15 ,  G11B2220/2516

Abstract: Timing recovery optimization using disk clock. A novel means is presented to perform and provide control of the sampling frequency of a signal that is read from a disk within a hard disk drive (HDD). Two separate, yet somewhat cooperating control loops are employed to provide feedback control of the sampling frequency of the signal that is read from disk. A timing recovery loop and a disk clock loop operate in conjunction with one another according to some desired manner (which can be predetermined or adaptive) to ensure that the sampling of the signal is performed to a very accurate degree. In one implementation, the timing recovery loop governs the sampling rate until the disk clock loop has locked, from which time either the disk clock loop govern the sampling or some combination of the signals provided from the two loops govern the sampling.

Abstract translation: 使用磁盘时钟的定时恢复优化。 提出了一种新颖的方法来执行并提供从硬盘驱动器（HDD）中的盘读取的信号的采样频率的控制。 采用两个单独的但有些协调的控制环来提供从盘读取的信号的采样频率的反馈控制。 定时恢复环路和磁盘时钟环路根据一些期望的方式（可以是预定的或自适应的）相互协同操作，以确保以非常准确的程度执行信号的采样。 在一个实现中，定时恢复循环控制采样速率，直到磁盘时钟循环锁定为止，从此时间盘时钟环控制采样或从两个循环提供的信号的某些组合控制采样。

公开(公告)号：US07864464B2

公开(公告)日：2011-01-04

申请号：US12648746

申请日：2009-12-29

Applicant: William Gene Bliss ,  Thomas V. Souvignier

Inventor： William Gene Bliss ,  Thomas V. Souvignier

IPC: G11B5/02

CPC classification number: G11B5/09 ,  G11B20/10009 ,  G11B20/10046 ,  G11B20/10222 ,  G11B20/10425 ,  G11B2220/2516

Abstract: A system reads data from a magnetic storage media. A read head reads data from the magnetic storage media and produce an analog signal. A variable gain amplifier amplifies the analog signal. An offset adjust module substantially centers the amplified analog signal to a midscale. A Magneto Resistive Asymmetry (MRA) correction module MRA corrects the amplified analog signal. A Continuous Time Filter (CTF) compensation module processes the amplified analog signal. An Analog to Digital Converter (ADC) samples the amplified analog signal based upon a control signal to produce a digital signal. A Disk Lock Clock (DLC) system produces the control signal to the ADC. The control signal is representative of a frequency offset caused by at least one servo wedge rate error. A Finite Impulse Response (FIR) filter module filters the digital signal. A sequence detector processes the digital signal and detects a bit sequence from the digital signal.

Abstract translation: 系统从磁存储介质读取数据。 读头从磁存储介质读取数据并产生模拟信号。 可变增益放大器放大模拟信号。 偏移调整模块将放大的模拟信号基本上居中， 磁阻非对称（MRA）校正模块MRA校正放大的模拟信号。 连续时间滤波器（CTF）补偿模块处理放大的模拟信号。 模数转换器（ADC）根据控制信号对放大的模拟信号进行采样以产生数字信号。 磁盘锁定时钟（DLC）系统产生到ADC的控制信号。 控制信号表示由至少一个伺服楔速率误差引起的频率偏移。 有限脉冲响应（FIR）滤波器模块对数字信号进行滤波。 序列检测器处理数字信号并从数字信号中检测位序列。