公开(公告)号：US09379059B2

公开(公告)日：2016-06-28

申请号：US13286231

申请日：2011-11-01

申请人： Ching-Chung Ko ,  Tao Cheng ,  Tien-Yueh Liu ,  Ta-Hsi Chou ,  Peng-Cheng Kao ,  Ling-Wei Ke

发明人： Ching-Chung Ko ,  Tao Cheng ,  Tien-Yueh Liu ,  Ta-Hsi Chou ,  Peng-Cheng Kao ,  Ling-Wei Ke

IPC分类号： H01L27/10 ,  H01L23/528 ,  H01L21/8234

CPC分类号： H01L23/5286 ,  H01L21/823475 ,  H01L23/5226 ,  H01L23/53228 ,  H01L23/585 ,  H01L24/05 ,  H01L2224/05124 ,  H01L2924/0002 ,  H01L2924/14 ,  H01L2924/00

摘要： An integrated circuit chip includes a semiconductor substrate having thereon a plurality of IMD layers and a plurality of first conductive layers; a first passivation layer overlying the plurality of IMD layers and the first conductive layers; at least a first power/ground mesh wiring line in a first aluminum layer overlying the first Insulating layer; and at least a second power/ground mesh wiring line in a second aluminum layer overlying the first aluminum layer.

摘要翻译： 集成电路芯片包括其上具有多个IMD层和多个第一导电层的半导体衬底; 覆盖所述多个IMD层和所述第一导电层的第一钝化层; 在覆盖所述第一绝缘层的第一铝层中的至少第一电源/接地网布线; 以及覆盖在第一铝层上的第二铝层中的至少第二电源/接地网布线。

公开(公告)号：US08120067B1

公开(公告)日：2012-02-21

申请号：US13281458

申请日：2011-10-26

申请人： Ching-Chung Ko ,  Tao Cheng ,  Tien-Yueh Liu ,  Dar-Shii Chou ,  Peng-Cheng Kao

发明人： Ching-Chung Ko ,  Tao Cheng ,  Tien-Yueh Liu ,  Dar-Shii Chou ,  Peng-Cheng Kao

IPC分类号： H01L27/10

CPC分类号： H01L23/5286 ,  H01L2924/0002 ,  H01L2924/00

摘要： An integrated circuit chip includes a semiconductor substrate having thereon a plurality of IMD layers and first conductive layers embedded in the IMD layers; a first insulating layer overlying the IMD layers and the first conductive layers; a plurality of first power/ground mesh wiring lines, in a second conductive layer overlying the first insulating layer, for distributing power signal or ground signal; and a second insulating layer covering the second conductive layer and the first insulating layer.

摘要翻译： 集成电路芯片包括其上具有多个IMD层的半导体衬底和嵌入IMD层中的第一导电层; 覆盖IMD层和第一导电层的第一绝缘层; 多个第一电源/接地网状布线，位于覆盖所述第一绝缘层的第二导电层中，用于分配电力信号或接地信号; 以及覆盖所述第二导电层和所述第一绝缘层的第二绝缘层。

公开(公告)号：US20110001168A1

公开(公告)日：2011-01-06

申请号：US12883163

申请日：2010-09-15

申请人： Ching-Chung Ko ,  Tao Cheng ,  Tien-Yueh Liu ,  Dar-Shii Chou ,  Peng-Cheng Kao

发明人： Ching-Chung Ko ,  Tao Cheng ,  Tien-Yueh Liu ,  Dar-Shii Chou ,  Peng-Cheng Kao

IPC分类号： H01L23/52

CPC分类号： H01L23/5286 ,  H01L2924/0002 ,  H01L2924/00

摘要： An integrated circuit chip includes a semiconductor substrate having thereon a plurality of inter-metal dielectric (IMD) layers and a plurality of first conductive layers embedded in respective the plurality of IMD layers, wherein the first conductive layers comprise copper; a first passivation layer overlying the plurality of IMD layers and the plurality of first conductive layers; a plurality of first power/ground mesh wiring lines, formed in a second conductive layer overlying the first passivation layer, for distributing power signal or ground signal, wherein the second conductive layer comprise aluminum; and a second passivation layer covering the second conductive layer and the first passivation layer.

摘要翻译： 集成电路芯片包括其上具有多个金属间电介质（IMD）层的半导体衬底和嵌入在多个IMD层中的多个第一导电层，其中第一导电层包括铜; 覆盖所述多个IMD层和所述多个第一导电层的第一钝化层; 形成在覆盖所述第一钝化层的第二导电层中的多个第一电源/接地网布线，用于分配功率信号或接地信号，其中所述第二导电层包括铝; 以及覆盖所述第二导电层和所述第一钝化层的第二钝化层。

公开(公告)号：US06708312B1

公开(公告)日：2004-03-16

申请号：US10225284

申请日：2002-08-22

申请人： Ming-Mao Chiang ,  Ching-Chang Shih ,  Chin-Cho Tsai ,  Tien-Yueh Liu ,  Kuo-Chung Huang

发明人： Ming-Mao Chiang ,  Ching-Chang Shih ,  Chin-Cho Tsai ,  Tien-Yueh Liu ,  Kuo-Chung Huang

IPC分类号： A06F1750

CPC分类号： H01L22/20 ,  G06F17/5045 ,  H01L21/823892

摘要： A method for multi-threshold voltage CMOS process optimization. The method includes the steps of: providing a semiconductor substrate with a plurality of devices of different threshold voltages; establishing a plurality of types of timing models for a timing calculation; obtaining a static timing analysis report through the timing calculation; defining a large and a small setup time margin as a Tl and a Ts; changing the devices whose setup time margins are less than Ts to low threshold devices; changing the devices whose setup time margins are greater than Tl to high threshold devices; checking a setup time of each device; changing the devices whose setup time margin does not meet the enhanced static timing analysis report; performing a first pocket implant process for the normal threshold devices; performing a second pocket implant process for the low threshold devices and performing a third pocket implant process for the high threshold devices.

摘要翻译： 一种多阈值电压CMOS工艺优化的方法。 该方法包括以下步骤：向半导体衬底提供具有不同阈值电压的多个器件; 建立用于定时计算的多种类型的定时模型; 通过定时计算获得静态时序分析报告; 定义大的和小的建立时间裕度作为Tl和Ts; 将设置时间裕度小于Ts的设备更改为低阈值设备; 将设置时间裕度大于T1的设备更改为高阈值设备; 检查每个设备的设置时间; 更改设置时间间隔不符合增强静态时序分析报告的设备; 对正常阈值装置执行第一口袋注入工艺; 对所述低阈值装置执行第二口袋注入工艺，并对所述高阈值装置执行第三口袋注入工艺。

公开(公告)号：US08661388B2

公开(公告)日：2014-02-25

申请号：US12571576

申请日：2009-10-01

申请人： Tung-Chieh Chen ,  Ping-Hung Yu ,  Yao-Wen Chang ,  Fwu-Juh Huang ,  Tien-Yueh Liu

发明人： Tung-Chieh Chen ,  Ping-Hung Yu ,  Yao-Wen Chang ,  Fwu-Juh Huang ,  Tien-Yueh Liu

IPC分类号： G06F17/50

CPC分类号： G06F17/5072

摘要： A multi-packing tree (MPT) macro placer. The MPT macro placer comprises reading input files in a LEF/DEF format, creating a k-level binary multi-packing tree comprising k branch nodes each corresponding to one level and k+1 packing sub-trees each corresponding to one of the nodes and comprising a group of macros, optimizing the multi-packing tree according to a packing result thereof, and generating output files in a DEF format.

摘要翻译： 多包装树（MPT）宏放样器。 MPT宏放置器包括以LEF / DEF格式读取输入文件，创建包括k个分支节点的k级二进制多重打包树，每个k个分支节点对应于每个对应于一个节点的一个级别和k + 1个打包子树; 包括一组宏，根据其打包结果优化多包装树，并以DEF格式生成输出文件。

公开(公告)号：US20100023910A1

公开(公告)日：2010-01-28

申请号：US12571576

申请日：2009-10-01

申请人： Tung-Chieh Chen ,  Ping-Hung Yu ,  Yao-Wen Chang ,  Fwu-Juh Huang ,  Tien-Yueh Liu

发明人： Tung-Chieh Chen ,  Ping-Hung Yu ,  Yao-Wen Chang ,  Fwu-Juh Huang ,  Tien-Yueh Liu

IPC分类号： G06F17/50

CPC分类号： G06F17/5072

摘要： A multi-packing tree (MPT) macro placer. The MPT macro placer comprises reading input files in a LEF/DEF format, creating a k-level binary multi-packing tree comprising k branch nodes each corresponding to one level and k+1 packing sub-trees each corresponding to one of the nodes and comprising a group of macros, optimizing the multi-packing tree according to a packing result thereof, and generating output files in a DEF format.

摘要翻译： 多包装树（MPT）宏放样器。 MPT宏放置器包括以LEF / DEF格式读取输入文件，创建包括k个分支节点的k级二进制多重打包树，每个k个分支节点对应于每个对应于一个节点的一个级别和k + 1个打包子树; 包括一组宏，根据其打包结果优化多包装树，并以DEF格式生成输出文件。

公开(公告)号：US20080023792A1

公开(公告)日：2008-01-31

申请号：US11460641

申请日：2006-07-28

申请人： Tien-Yueh Liu ,  Hsiu-Chen Peng

发明人： Tien-Yueh Liu ,  Hsiu-Chen Peng

IPC分类号： H01L29/00

CPC分类号： H01L27/0207 ,  G06F17/5072 ,  H01L27/0623 ,  H01L27/11807

摘要： Embodiments of the invention provide a layout architecture for a standard cell integrated circuit having an array of logic cells. A plurality of first power rails is above a substrate, each of the first power rails being coupled to a power supply and extending across the logic cells. Adjacent first power rails are coupled to different voltage supplies. A filler capacitor is positioned beneath three or more adjacent first power rails and coupled to first and second voltage supplies. The filler capacitor comprises a first MOS capacitor formed with a first gate overlapping a first base in a first active region, the first gate coupled to the first voltage supply and the first base coupled to the second voltage supply. A middle first power rail of the three or more adjacent first power rails extends across the first active region.

摘要翻译： 本发明的实施例提供了具有逻辑单元阵列的标准单元集成电路的布局架构。 多个第一电力轨道在衬底之上，每个第一电力轨耦合到电源并且跨越逻辑单元延伸。 相邻的第一个电源轨耦合到不同的电源。 填充电容器位于三个或更多个相邻的第一电源轨下方并且耦合到第一和第二电压源。 填充电容器包括形成有第一栅极的第一MOS电容器，第一栅极与第一有源区域中的第一基极重叠，第一栅极耦合到第一电压源，第一基极耦合到第二电压源。 三个或更多相邻的第一电力轨的中间第一电力轨延伸穿过第一有源区。

公开(公告)号：US20090236637A1

公开(公告)日：2009-09-24

申请号：US12052735

申请日：2008-03-21

申请人： Ching-Chung Ko ,  Tao Cheng ,  Tien-Yueh Liu ,  Dar-Shii Chou ,  Peng-Cheng Kao

发明人： Ching-Chung Ko ,  Tao Cheng ,  Tien-Yueh Liu ,  Dar-Shii Chou ,  Peng-Cheng Kao

IPC分类号： H01L27/10

CPC分类号： H01L23/5286 ,  H01L2924/0002 ,  H01L2924/00

摘要： An integrated circuit chip with reduced IR drop and improved chip performance is disclosed. The integrated circuit chip includes a semiconductor substrate having thereon a plurality of inter-metal dielectric (IMD) layers and a plurality of copper metal layers embedded in respective the plurality of IMD layers; a first passivation layer overlying the plurality of IMD layers and the plurality of copper metal layers; a first power/ground ring of a circuit block of the integrated circuit chip formed in a topmost layer of the plurality of copper metal layers; a second power/ground ring of the circuit block of the integrated circuit chip formed in an aluminum layer over the first passivation layer; and a second passivation layer covering the second power/ground ring and the first passivation layer.

摘要翻译： 公开了具有降低的IR降低和芯片性能改善的集成电路芯片。 集成电路芯片包括其上具有多个金属间电介质（IMD）层和嵌入在多个IMD层中的多个铜金属层的半导体衬底; 覆盖所述多个IMD层和所述多个铜金属层的第一钝化层; 所述集成电路芯片的电路块的第一电源/接地环形成在所述多个铜金属层的最上层中; 所述集成电路芯片的电路块的第二电源/接地环形成在所述第一钝化层上的铝层中; 以及覆盖所述第二电源/接地环和所述第一钝化层的第二钝化层。

公开(公告)号：US20070157146A1

公开(公告)日：2007-07-05

申请号：US11608417

申请日：2006-12-08

申请人： Tung-Chieh Chen ,  Ping-Hung Yu ,  Yao-Wen Chang ,  Fwu-Juh Huang ,  Tien-Yueh Liu

发明人： Tung-Chieh Chen ,  Ping-Hung Yu ,  Yao-Wen Chang ,  Fwu-Juh Huang ,  Tien-Yueh Liu

IPC分类号： G06F17/50 ,  H01L25/00 ,  H03K19/00

CPC分类号： G06F17/5072

摘要： A multi-packing tree (MPT) macro placer. The MPT macro placer comprises reading input files in a LEF/DEF format, creating a k-level binary multi-packing tree comprising k branch nodes each corresponding to one level and k+1 packing sub-trees each corresponding to one of the nodes and comprising a group of macros, optimizing the multi-packing tree according to a packing result thereof, and generating output files in a DEF format.

摘要翻译： 多包装树（MPT）宏放样器。 MPT宏放置器包括以LEF / DEF格式读取输入文件，创建包括k个分支节点的k级二进制多重打包树，每个k个分支节点对应于每个对应于一个节点的一个级别和k + 1个打包子树; 包括一组宏，根据其打包结果优化多包装树，并以DEF格式生成输出文件。

公开(公告)号：US20120038055A1

公开(公告)日：2012-02-16

申请号：US13281458

申请日：2011-10-26

申请人： Ching-Chung Ko ,  Tao Cheng ,  Tien-Yueh Liu ,  Dar-Shii Chou ,  Peng-Cheng Kao

发明人： Ching-Chung Ko ,  Tao Cheng ,  Tien-Yueh Liu ,  Dar-Shii Chou ,  Peng-Cheng Kao

IPC分类号： H01L23/535

CPC分类号： H01L23/5286 ,  H01L2924/0002 ,  H01L2924/00

摘要： An integrated circuit chip includes a semiconductor substrate having thereon a plurality of IMD layers and first conductive layers embedded in the IMD layers; a first insulating layer overlying the IMD layers and the first conductive layers; a plurality of first power/ground mesh wiring lines, in a second conductive layer overlying the first Insulating layer, for distributing power signal or ground signal; and a second insulating layer covering the second conductive layer and the first insulating layer.

摘要翻译： 集成电路芯片包括其上具有多个IMD层的半导体衬底和嵌入IMD层中的第一导电层; 覆盖IMD层和第一导电层的第一绝缘层; 在覆盖所述第一绝缘层的第二导电层中的多个第一电源/接地网状布线，用于分配电力信号或接地信号; 以及覆盖所述第二导电层和所述第一绝缘层的第二绝缘层。