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    Method for multi-threshold voltage CMOS process optimization
    1.
    发明授权
    Method for multi-threshold voltage CMOS process optimization 有权
    多阈值电压CMOS工艺优化方法

    公开(公告)号：US06708312B1

    公开(公告)日：2004-03-16

    申请号：US10225284

    申请日：2002-08-22

    申请人： Ming-Mao Chiang ,  Ching-Chang Shih ,  Chin-Cho Tsai ,  Tien-Yueh Liu ,  Kuo-Chung Huang

    发明人： Ming-Mao Chiang ,  Ching-Chang Shih ,  Chin-Cho Tsai ,  Tien-Yueh Liu ,  Kuo-Chung Huang

    IPC分类号： A06F1750

    CPC分类号： H01L22/20 ,  G06F17/5045 ,  H01L21/823892

    摘要： A method for multi-threshold voltage CMOS process optimization. The method includes the steps of: providing a semiconductor substrate with a plurality of devices of different threshold voltages; establishing a plurality of types of timing models for a timing calculation; obtaining a static timing analysis report through the timing calculation; defining a large and a small setup time margin as a Tl and a Ts; changing the devices whose setup time margins are less than Ts to low threshold devices; changing the devices whose setup time margins are greater than Tl to high threshold devices; checking a setup time of each device; changing the devices whose setup time margin does not meet the enhanced static timing analysis report; performing a first pocket implant process for the normal threshold devices; performing a second pocket implant process for the low threshold devices and performing a third pocket implant process for the high threshold devices.

    摘要翻译： 一种多阈值电压CMOS工艺优化的方法。 该方法包括以下步骤：向半导体衬底提供具有不同阈值电压的多个器件; 建立用于定时计算的多种类型的定时模型; 通过定时计算获得静态时序分析报告; 定义大的和小的建立时间裕度作为Tl和Ts; 将设置时间裕度小于Ts的设备更改为低阈值设备; 将设置时间裕度大于T1的设备更改为高阈值设备; 检查每个设备的设置时间; 更改设置时间间隔不符合增强静态时序分析报告的设备; 对正常阈值装置执行第一口袋注入工艺; 对所述低阈值装置执行第二口袋注入工艺，并对所述高阈值装置执行第三口袋注入工艺。

    Computer graphics memory architecture having a graphics processor and a buffer
    2.
    发明授权
    Computer graphics memory architecture having a graphics processor and a buffer 失效
    具有图形处理器和缓冲器的计算机图形存储器架构

    公开(公告)号：US5946005A

    公开(公告)日：1999-08-31

    申请号：US920139

    申请日：1997-08-27

    申请人： Ming-Mao Chiang ,  Ruen-Rone Lee ,  Ming-Fen Lin

    发明人： Ming-Mao Chiang ,  Ruen-Rone Lee ,  Ming-Fen Lin

    IPC分类号： G06T15/00 ,  G09G5/36

    CPC分类号： G06T15/005

    摘要： Disclosed is an improved computer graphics memory architecture. The architecture includes an address translation table (ATT) and a buffer. The address translation table receives information about desired pixel data and determines the physical address of the desired data. The buffer is connected to the ATT and has a dual bank which stores the color value and the Z value of a 3-D pixel. A buffer addressing method is also provided in which the address of the desired pixel information and associated control circuits may be quickly determined through an appropriate data arrangement in the buffer and an address transfer table.

    摘要翻译： 公开了一种改进的计算机图形存储器架构。 该架构包括地址转换表（ATT）和缓冲区。 地址转换表接收关于期望像素数据的信息，并确定所需数据的物理地址。 缓冲器连接到ATT，并具有存储3-D像素的颜色值和Z值的双存储体。 还提供了缓冲器寻址方法，其中可以通过缓冲器中的适当数据布置和地址传送表来快速确定期望像素信息和相关控制电路的地址。