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公开(公告)号：US20050125756A1
公开(公告)日：2005-06-09
申请号：US10707286
申请日：2003-12-03
申请人： Gary Ditlow , Daria Dooling , Timothy Dunham , William Leipold , Stephen Thomas , Ralph Williams
发明人： Gary Ditlow , Daria Dooling , Timothy Dunham , William Leipold , Stephen Thomas , Ralph Williams
CPC分类号： G06F17/5072
摘要： Disclosed is a method and structure that partitions an integrated circuit design by identifying logical blocks within the integrated circuit design based on size heuristics of logical macros in the design hierarchy. The invention determines whether the number of logical blocks is within a range of desired number of logical blocks and repeats the process of identifying logical blocks for different hierarchical levels of the integrated circuit design until the number of logical blocks is within the range of the desired number of logical blocks. This serves as a guide to partition the chip as opposed to a grid-like partitioning.
摘要翻译： 公开了通过基于设计层级中的逻辑宏的大小启发式来识别集成电路设计中的逻辑块来分割集成电路设计的方法和结构。 本发明确定逻辑块的数量是否在期望数量的逻辑块的范围内，并重复识别用于集成电路设计的不同层级的逻辑块的处理，直到逻辑块的数量在所需数量的范围内 的逻辑块。 这作为分配芯片的指南，而不是格栅分割。
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公开(公告)号：US20060081988A1
公开(公告)日：2006-04-20
申请号：US11256025
申请日：2005-10-21
申请人： Timothy Dunham , Ezra Hall , Howard Landis , Mark Lavin , William Leipold
发明人： Timothy Dunham , Ezra Hall , Howard Landis , Mark Lavin , William Leipold
IPC分类号： H01L23/48
CPC分类号： H01L23/522 , H01L23/5226 , H01L23/528 , H01L2924/0002 , H01L2924/00
摘要： An interconnect structure, method of fabricating the interconnect structure and method of designing the interconnect structure for use in semiconductor devices. The interconnect structure includes a damascene metal wire having a pattern of dielectric filled holes.
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公开(公告)号：US20080104555A1
公开(公告)日：2008-05-01
申请号：US11947254
申请日：2007-11-29
申请人： David DeMaris , Timothy Dunham , William Leipold , Daniel Maynard , Michael Scaman , Shi Zhong
发明人： David DeMaris , Timothy Dunham , William Leipold , Daniel Maynard , Michael Scaman , Shi Zhong
IPC分类号： G06F17/50
摘要： A computer program product for generating test patterns for a pattern sensitive algorithm. The program product includes code for extracting feature samples from a layout design; grouping feature samples into clusters; selecting at least one area from the layout design that covers a feature sample from each cluster; and saving each pattern layout covered by the at least one area as test patterns.
摘要翻译： 一种用于生成模式敏感算法的测试模式的计算机程序产品。 程序产品包括从布局设计中提取特征样本的代码; 将特征样本分组成簇; 从布局设计中选择至少一个覆盖每个聚类的特征样本的区域; 并且将至少一个区域覆盖的每个模式布局保存为测试模式。
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公开(公告)号：US20080019585A1
公开(公告)日：2008-01-24
申请号：US11776769
申请日：2007-07-12
IPC分类号： G06K9/00
CPC分类号： G06F17/5068 , G03F1/68
摘要： A method for reducing a number of shapes, and a computer readable program code adapted to perform said method. The method forms first and second shape patterns. The second shape pattern includes the first shape pattern and error shapes. The error shapes are extracted from the second shape pattern. At least one environment shape corresponding to each error shape is derived from a subset of the error shapes. For example, each error shape in the subset may be expanded to form a corresponding expanded shape, and at least one environment shape corresponding to each expanded shape may be formed by removing all portions of the expanded shape common to the second shape pattern. The environment shape reflects a local geometric environment of its corresponding error shape. A subset of the environment shapes are deleted such that only unique environment shapes satisfying a selection criterion remain.
摘要翻译： 一种用于减少形状的方法，以及适于执行所述方法的计算机可读程序代码。 该方法形成第一和第二形状图案。 第二形状图案包括第一形状图案和错误形状。 从第二形状图案提取错误形状。 从错误形状的子集中导出与每个错误形状对应的至少一个环境形状。 例如，子集中的每个错误形状可以被扩展以形成对应的扩展形状，并且可以通过去除与第二形状图案相同的扩展形状的所有部分来形成与每个扩展形状对应的至少一个环境形状。 环境形状反映了其相应错误形状的局部几何环境。 环境形状的一个子集被删除，使得仅保持满足选择标准的独特环境形状。
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公开(公告)号：US20070273048A1
公开(公告)日：2007-11-29
申请号：US11837723
申请日：2007-08-13
申请人： Timothy Dunham , Ezra Hall , Howard Landis , Mark Lavin , William Leipold
发明人： Timothy Dunham , Ezra Hall , Howard Landis , Mark Lavin , William Leipold
IPC分类号： H01L23/48
CPC分类号： H01L23/522 , H01L23/5226 , H01L23/528 , H01L2924/0002 , H01L2924/00
摘要： An interconnect structure, method of fabricating the interconnect structure and method of designing the interconnect structure for use in semiconductor devices. The interconnect structure includes a damascene metal wire having a pattern of dielectric filled holes.
摘要翻译： 互连结构，制造互连结构的方法以及设计用于半导体器件的互连结构的方法。 互连结构包括具有电介质填充孔图案的镶嵌金属线。
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6.发明申请System and method for testing pattern sensitive algorithms for semiconductor design 有权用于半导体设计测试模式敏感算法的系统和方法公开(公告)号：US20070038970A1
公开(公告)日：2007-02-15
申请号：US11202591
申请日：2005-08-12
申请人： David DeMaris , Timothy Dunham , William Leipold , Daniel Maynard , Michael Scaman , Shi Zhong
发明人： David DeMaris , Timothy Dunham , William Leipold , Daniel Maynard , Michael Scaman , Shi Zhong
IPC分类号： G06F17/50
摘要： A system and method for generating test patterns for a pattern sensitive algorithm. The method comprises the steps extracting feature samples from a layout design; grouping feature samples into clusters; selecting at least one area from the layout design that covers a feature sample from each cluster; and saving each pattern layout covered by the at least one area as test patterns.
摘要翻译： 一种用于生成模式敏感算法的测试模式的系统和方法。 该方法包括从布局设计中提取特征样本的步骤; 将特征样本分组成簇; 从布局设计中选择至少一个覆盖每个聚类的特征样本的区域; 并且将至少一个区域覆盖的每个模式布局保存为测试模式。
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公开(公告)号：US20070275551A1
公开(公告)日：2007-11-29
申请号：US11837768
申请日：2007-08-13
申请人： Timothy Dunham , Ezra Hall , Howard Landis , Mark Lavin , William Leipold
发明人： Timothy Dunham , Ezra Hall , Howard Landis , Mark Lavin , William Leipold
IPC分类号： H01L21/4763
CPC分类号： H01L23/522 , H01L23/5226 , H01L23/528 , H01L2924/0002 , H01L2924/00
摘要： An interconnect structure, method of fabricating the interconnect structure and method of designing the interconnect structure for use in semiconductor devices. The interconnect structure includes a damascene metal wire having a pattern of dielectric filled holes.
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