利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

10 条记录 (耗时 0.044 秒)

    SYSTEM FOR SEARCH AND ANALYSIS OF SYSTEMATIC DEFECTS IN INTEGRATED CIRCUITS
    3.
    发明申请
    SYSTEM FOR SEARCH AND ANALYSIS OF SYSTEMATIC DEFECTS IN INTEGRATED CIRCUITS 有权
    集成电路系统缺陷的搜索与分析系统

    公开(公告)号：US20070211933A1

    公开(公告)日：2007-09-13

    申请号：US11748575

    申请日：2007-05-15

    申请人： Bette Reuter ,  David DeMaris ,  Mark Lavin ,  William Leipold ,  Daniel Maynard ,  Maharaj Mukherjee

    发明人： Bette Reuter ,  David DeMaris ,  Mark Lavin ,  William Leipold ,  Daniel Maynard ,  Maharaj Mukherjee

    IPC分类号： G06K9/00

    CPC分类号： G06T7/001 ,  G06T2207/30148

    摘要： Disclosed is a method of locating systematic defects in integrated circuits. The invention first performs a preliminary extracting and index processing of the circuit design and then performs feature searching. When performing the preliminary extracting and index processing the invention establishes a window grid for the circuit design and merges basis patterns with shapes in the circuit design within each window of the window grid. The invention transforms shapes in a each window into feature vectors by finding intersections between the basis patterns and the shapes in the windows. Then, the invention clusters the feature vectors to produce an index of feature vectors. After performing the extracting and index processing, the invention performs the process of feature searching by first identifying a defect region window of the circuit layout and similarly merging basis patterns with shapes in the defect region window. This merging process can include rotating and mirroring the shapes in the defect region. The invention similarly transforms shapes in the defect region window into defect vectors by finding intersections between basis patterns and the shapes in the defect region. Then, the invention can easily find feature vectors that are similar to the defect vector using, for example, representative feature vectors from the index of feature vectors. Then, the similarities and differences between the defect vectors and the feature vectors can be analyzed.

    摘要翻译： 公开了一种定位集成电路系统缺陷的方法。 本发明首先进行电路设计的初步提取和索引处理，然后执行特征搜索。 当执行初步提取和索引处理时，本发明建立了用于电路设计的窗口网格，并且将窗体网格的每个窗口内的电路设计中的形状与基本图案合并。 本发明通过在窗口中找到基本图案和形状之间的交点来将每个窗口中的形状转换为特征向量。 然后，本发明聚集特征向量以产生特征向量的索引。 在执行提取和索引处理之后，本发明通过首先识别电路布局的缺陷区域窗口并且将基本模式与缺陷区域窗口中的形状类似地合并来执行特征搜索的处理。 该合并过程可以包括旋转和镜像缺陷区域中的形状。 本发明类似地通过在缺陷区域中找到基础图案和形状之间的交点来将缺陷区域窗口中的形状转换为缺陷向量。 然后，本发明可以使用例如来自特征向量的索引的代表性特征向量容易地找到与缺陷向量相似的特征向量。 然后，可以分析缺陷向量和特征向量之间的相似性和差异。

    SYSTEM FOR SEARCH AND ANALYSIS OF SYSTEMATIC DEFECTS IN INTEGRATED CIRCUITS
    5.
    发明申请
    SYSTEM FOR SEARCH AND ANALYSIS OF SYSTEMATIC DEFECTS IN INTEGRATED CIRCUITS 有权
    集成电路系统缺陷的搜索与分析系统

    公开(公告)号：US20050094863A1

    公开(公告)日：2005-05-05

    申请号：US10605849

    申请日：2003-10-30

    申请人： Bette Bergman Reuter ,  David DeMaris ,  Mark Lavin ,  William Leipold ,  Daniel Maynard ,  Maharaj Mukherjee

    发明人： Bette Bergman Reuter ,  David DeMaris ,  Mark Lavin ,  William Leipold ,  Daniel Maynard ,  Maharaj Mukherjee

    IPC分类号： G06K9/00 ,  G06T7/00

    CPC分类号： G06T7/001 ,  G06T2207/30148

    摘要： Disclosed is a method of locating systematic defects in integrated circuits. The invention first performs a preliminary extracting and index processing of the circuit design and then performs feature searching. When performing the preliminary extracting and index processing the invention establishes a window grid for the circuit design and merges basis patterns with shapes in the circuit design within each window of the window grid. The invention transforms shapes in a each window into feature vectors by finding intersections between the basis patterns and the shapes in the windows. Then, the invention clusters the feature vectors to produce an index of feature vectors. After performing the extracting and index processing, the invention performs the process of feature searching by first identifying a defect region window of the circuit layout and similarly merging basis patterns with shapes in the defect region window. This merging process can include rotating and mirroring the shapes in the defect region. The invention similarly transforms shapes in the defect region window into defect vectors by finding intersections between basis patterns and the shapes in the defect region. Then, the invention can easily find feature vectors that are similar to the defect vector using, for example, representative feature vectors from the index of feature vectors. Then, the similarities and differences between the defect vectors and the feature vectors can be analyzed.

    摘要翻译： 公开了一种定位集成电路系统缺陷的方法。 本发明首先进行电路设计的初步提取和索引处理，然后执行特征搜索。 当执行初步提取和索引处理时，本发明建立了用于电路设计的窗口网格，并且将窗体网格的每个窗口内的电路设计中的形状与基本图案合并。 本发明通过在窗口中找到基本图案和形状之间的交点来将每个窗口中的形状转换为特征向量。 然后，本发明聚集特征向量以产生特征向量的索引。 在执行提取和索引处理之后，本发明通过首先识别电路布局的缺陷区域窗口并且将基本模式与缺陷区域窗口中的形状类似地合并来执行特征搜索的处理。 该合并过程可以包括旋转和镜像缺陷区域中的形状。 本发明类似地通过在缺陷区域中找到基础图案和形状之间的交点来将缺陷区域窗口中的形状转换为缺陷向量。 然后，本发明可以使用例如来自特征向量的索引的代表性特征向量容易地找到与缺陷向量相似的特征向量。 然后，可以分析缺陷向量和特征向量之间的相似性和差异。

    CONTENT BASED YIELD PREDICTION OF VLSI DESIGNS
    6.
    发明申请
    CONTENT BASED YIELD PREDICTION OF VLSI DESIGNS 有权
    基于内容的VLSI设计预测

    公开(公告)号：US20060253806A1

    公开(公告)日：2006-11-09

    申请号：US10908342

    申请日：2005-05-09

    申请人： Robert Allen ,  Daria Dooling ,  Jason Hibbeler ,  Daniel Maynard ,  Sarah Prue ,  Ralph Williams

    发明人： Robert Allen ,  Daria Dooling ,  Jason Hibbeler ,  Daniel Maynard ,  Sarah Prue ,  Ralph Williams

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5045

    摘要： A system, method and program product for predicting yield of a VLSI design. A method is providing including the steps of: identifying and grouping sub-circuits contained within an integrated circuit design by type; calculating critical area values for regions within the integrated circuit design; and applying different yield models to critical area values based on the types of the regions used to calculate the critical area values, wherein each yield model is dependent on a type.

    摘要翻译： 一种用于预测VLSI设计产量的系统，方法和程序产品。 一种提供方法包括以下步骤：通过类型识别和分组集成电路设计中包含的子电路; 计算集成电路设计中区域的关键面积值; 以及基于用于计算临界面积值的区域的类型将不同的屈服模型应用于临界区域值，其中每个产量模型依赖于类型。

    YIELD OPTIMIZATION IN ROUTER FOR SYSTEMATIC DEFECTS
    7.
    发明申请
    YIELD OPTIMIZATION IN ROUTER FOR SYSTEMATIC DEFECTS 失效
    系统缺陷路由器的优化优化

    公开(公告)号：US20070240090A1

    公开(公告)日：2007-10-11

    申请号：US11279262

    申请日：2006-04-11

    申请人： Jeanne Bickford ,  Markus Buehler ,  Jason Hibbeler ,  Juergen Koehl ,  Daniel Maynard

    发明人： Jeanne Bickford ,  Markus Buehler ,  Jason Hibbeler ,  Juergen Koehl ,  Daniel Maynard

    IPC分类号： G06F17/50 ,  G06F19/00

    CPC分类号： G06F17/5077

    摘要： Embodiments herein provide a method and computer program product for optimizing router settings to increase IC yield. A method begins by reviewing yield data in an IC manufacturing line to identify structure-specific mechanisms that impact IC yield. Next, the method establishes a structural identifier for each structure-specific mechanism, wherein the structural identifiers include wire codes, tags, and/or unique identifiers. Different structural identifiers are established for wires having different widths. Furthermore, the method establishes a weighting factor for each structure-specific mechanism, wherein higher weighting factors are established for structure-specific mechanisms comprising thick wires proximate to multiple thick wires. The method establishes the structural identifiers and the weighting factors for incidence of spacing between single wide lines, double wide lines, and triple wide lines and for incidence of wires above large metal lands. Subsequently, the router settings are modified based on the structural identifiers and the weighting factors to minimize systematic defects.

    摘要翻译： 本文的实施例提供了一种用于优化路由器设置以增加IC产量的方法和计算机程序产品。 一种方法开始于检查IC生产线中的产量数据，以确定影响IC产量的结构特异性机制。 接下来，该方法为每个结构特定机制建立结构标识符，其中结构标识符包括有线代码，标签和/或唯一标识符。 针对具有不同宽度的电线建立了不同的结构标识符。 此外，该方法为每个结构特定机构建立加权因子，其中针对包括靠近多个粗线的粗线的结构特定机构建立较高的加权因子。 该方法建立了单宽线，双宽线和三宽线之间的间距发生的结构标识符和加权因子，以及大金属土地上电线的入射。 随后，路由器设置基于结构标识符和权重因子进行修改，以最大限度地减少系统缺陷。

    METHOD AND SYSTEM FOR IMPROVING INTEGRATED CIRCUIT MANUFACTURING PRODUCTIVITY
    8.
    发明申请
    METHOD AND SYSTEM FOR IMPROVING INTEGRATED CIRCUIT MANUFACTURING PRODUCTIVITY 失效
    改进集成电路制造生产力的方法和系统

    公开(公告)号：US20050278663A1

    公开(公告)日：2005-12-15

    申请号：US10709807

    申请日：2004-05-28

    申请人： Douglas Kemerer ,  Daniel Maynard ,  Gustavo Tellez ,  Lijiang Wang ,  Peter Wissell

    发明人： Douglas Kemerer ,  Daniel Maynard ,  Gustavo Tellez ,  Lijiang Wang ,  Peter Wissell

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5081 ,  G06F2217/12 ,  Y02P90/265

    摘要： A method and a system for improving manufacturing productivity of an integrated circuit. The method including: (a) generating a set of physical design rules, (b) assigning a rule scoring equation to each physical design rule of the set of physical design rules; (c) checking a physical design of the integrated circuit for deviations from each design rule; (d) computing a score for each physical design rule, using the corresponding rule scoring equation assigned to each physical design rule, for which one or more deviations were found in step (c); and (e) computing a productivity score for the integrated circuit design based on the scores computed in step (d).

    摘要翻译： 一种用于提高集成电路的制造生产率的方法和系统。 该方法包括：（a）生成一组物理设计规则，（b）将规则评分方程分配给所述一组物理设计规则的每个物理设计规则; （c）检查集成电路的物理设计以偏离每个设计规则; （d）使用分配给每个物理设计规则的相应规则评分方程计算每个物理设计规则的分数，在步骤（c）中发现一个或多个偏差; 以及（e）基于步骤（d）中计算出的分数计算集成电路设计的生产率得分。

    IC DESIGN MODELING ALLOWING DIMENSION-DEPENDENT RULE CHECKING
    9.
    发明申请
    IC DESIGN MODELING ALLOWING DIMENSION-DEPENDENT RULE CHECKING 失效
    IC设计建模允许尺寸依赖规则检查

    公开(公告)号：US20080059929A1

    公开(公告)日：2008-03-06

    申请号：US11926289

    申请日：2007-10-29

    申请人： Evanthia Papadopoulou ,  Daniel Maynard

    发明人： Evanthia Papadopoulou ,  Daniel Maynard

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5081

    摘要： A method, system and program product to model an IC design to include dimensions such as a local width and spacing of IC shapes in a consistent fashion. In particular, the invention uses a core portion of Voronoi diagrams to partition edges of a shape into intervals and assigns at least one dimension to each interval such as a local width and spacing. Dimension assignment can be made as any desirable definition set for width and spacing, e.g., numerical values or continuous dimension-dependent design rules. Design rule checking for dimension-dependent spacing rules given in any arbitrary functional form of width and spacing is possible. Application of the invention can be made anywhere the width and spacing of VLSI shapes play a role, e.g., relative to a single edge, neighboring edges, neighboring shapes, and/or for edges in more than one layer of the IC design.

    摘要翻译： 一种用于对IC设计进行建模的方法，系统和程序产品，以一致的方式包括诸如局部宽度和IC形状间隔的尺寸。 特别地，本发明使用Voronoi图的核心部分将形状的边缘划分成间隔，并且为每个间隔分配至少一个维度，例如局部宽度和间隔。 尺寸分配可以作为针对宽度和间距设置的任何期望的定义，例如数值或连续尺寸依赖的设计规则。 设计规则检查以尺寸为依据的间距规则，以宽度和间距的任意功能形式给出是可能的。 本发明的应用可以在VLSI形状的宽度和间距例如相对于单个边缘，相邻边缘，相邻形状和/或针对IC设计的多于一个层中的边缘发挥作用的任何地方进行。

    IC design modeling allowing dimension-dependent rule checking
    10.
    发明申请
    IC design modeling allowing dimension-dependent rule checking 有权
    IC设计建模允许维度依赖的规则检查

    公开(公告)号：US20050172247A1

    公开(公告)日：2005-08-04

    申请号：US10708039

    申请日：2004-02-04

    申请人： Evanthia Papadopoulou ,  Daniel Maynard

    发明人： Evanthia Papadopoulou ,  Daniel Maynard

    IPC分类号： G06F9/45 ,  G06F17/50

    CPC分类号： G06F17/5081

    摘要： A method, system and program product to model an IC design to include dimensions such as a local width and spacing of IC shapes in a consistent fashion. In particular, the invention uses a core portion of Voronoi diagrams to partition edges of a shape into intervals and assigns at least one dimension to each interval such as a local width and spacing. Dimension assignment can be made as any desirable definition set for width and spacing, e.g., numerical values or continuous dimension-dependent design rules. Design rule checking for dimension-dependent spacing rules given in any arbitrary functional form of width and spacing is possible. Application of the invention can be made anywhere the width and spacing of VLSI shapes play a role, e.g., relative to a single edge, neighboring edges, neighboring shapes, and/or for edges in more than one layer of the IC design.

    摘要翻译： 一种用于对IC设计进行建模的方法，系统和程序产品，以一致的方式包括诸如局部宽度和IC形状间隔的尺寸。 特别地，本发明使用Voronoi图的核心部分将形状的边缘划分成间隔，并且为每个间隔分配至少一个维度，例如局部宽度和间隔。 尺寸分配可以作为针对宽度和间距设置的任何期望的定义，例如数值或连续尺寸依赖的设计规则。 设计规则检查以尺寸为依据的间距规则，以宽度和间距的任意功能形式给出是可能的。 本发明的应用可以在VLSI形状的宽度和间距例如相对于单个边缘，相邻边缘，相邻形状和/或针对IC设计的多于一个层中的边缘发挥作用的任何地方进行。