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    SYSTEM FOR SEARCH AND ANALYSIS OF SYSTEMATIC DEFECTS IN INTEGRATED CIRCUITS
    4.
    发明申请
    SYSTEM FOR SEARCH AND ANALYSIS OF SYSTEMATIC DEFECTS IN INTEGRATED CIRCUITS 有权
    集成电路系统缺陷的搜索与分析系统

    公开(公告)号：US20070211933A1

    公开(公告)日：2007-09-13

    申请号：US11748575

    申请日：2007-05-15

    申请人： Bette Reuter ,  David DeMaris ,  Mark Lavin ,  William Leipold ,  Daniel Maynard ,  Maharaj Mukherjee

    发明人： Bette Reuter ,  David DeMaris ,  Mark Lavin ,  William Leipold ,  Daniel Maynard ,  Maharaj Mukherjee

    IPC分类号： G06K9/00

    CPC分类号： G06T7/001 ,  G06T2207/30148

    摘要： Disclosed is a method of locating systematic defects in integrated circuits. The invention first performs a preliminary extracting and index processing of the circuit design and then performs feature searching. When performing the preliminary extracting and index processing the invention establishes a window grid for the circuit design and merges basis patterns with shapes in the circuit design within each window of the window grid. The invention transforms shapes in a each window into feature vectors by finding intersections between the basis patterns and the shapes in the windows. Then, the invention clusters the feature vectors to produce an index of feature vectors. After performing the extracting and index processing, the invention performs the process of feature searching by first identifying a defect region window of the circuit layout and similarly merging basis patterns with shapes in the defect region window. This merging process can include rotating and mirroring the shapes in the defect region. The invention similarly transforms shapes in the defect region window into defect vectors by finding intersections between basis patterns and the shapes in the defect region. Then, the invention can easily find feature vectors that are similar to the defect vector using, for example, representative feature vectors from the index of feature vectors. Then, the similarities and differences between the defect vectors and the feature vectors can be analyzed.

    摘要翻译： 公开了一种定位集成电路系统缺陷的方法。 本发明首先进行电路设计的初步提取和索引处理，然后执行特征搜索。 当执行初步提取和索引处理时，本发明建立了用于电路设计的窗口网格，并且将窗体网格的每个窗口内的电路设计中的形状与基本图案合并。 本发明通过在窗口中找到基本图案和形状之间的交点来将每个窗口中的形状转换为特征向量。 然后，本发明聚集特征向量以产生特征向量的索引。 在执行提取和索引处理之后，本发明通过首先识别电路布局的缺陷区域窗口并且将基本模式与缺陷区域窗口中的形状类似地合并来执行特征搜索的处理。 该合并过程可以包括旋转和镜像缺陷区域中的形状。 本发明类似地通过在缺陷区域中找到基础图案和形状之间的交点来将缺陷区域窗口中的形状转换为缺陷向量。 然后，本发明可以使用例如来自特征向量的索引的代表性特征向量容易地找到与缺陷向量相似的特征向量。 然后，可以分析缺陷向量和特征向量之间的相似性和差异。

    SYSTEM FOR SEARCH AND ANALYSIS OF SYSTEMATIC DEFECTS IN INTEGRATED CIRCUITS
    6.
    发明申请
    SYSTEM FOR SEARCH AND ANALYSIS OF SYSTEMATIC DEFECTS IN INTEGRATED CIRCUITS 有权
    集成电路系统缺陷的搜索与分析系统

    公开(公告)号：US20050094863A1

    公开(公告)日：2005-05-05

    申请号：US10605849

    申请日：2003-10-30

    申请人： Bette Bergman Reuter ,  David DeMaris ,  Mark Lavin ,  William Leipold ,  Daniel Maynard ,  Maharaj Mukherjee

    发明人： Bette Bergman Reuter ,  David DeMaris ,  Mark Lavin ,  William Leipold ,  Daniel Maynard ,  Maharaj Mukherjee

    IPC分类号： G06K9/00 ,  G06T7/00

    CPC分类号： G06T7/001 ,  G06T2207/30148

    摘要： Disclosed is a method of locating systematic defects in integrated circuits. The invention first performs a preliminary extracting and index processing of the circuit design and then performs feature searching. When performing the preliminary extracting and index processing the invention establishes a window grid for the circuit design and merges basis patterns with shapes in the circuit design within each window of the window grid. The invention transforms shapes in a each window into feature vectors by finding intersections between the basis patterns and the shapes in the windows. Then, the invention clusters the feature vectors to produce an index of feature vectors. After performing the extracting and index processing, the invention performs the process of feature searching by first identifying a defect region window of the circuit layout and similarly merging basis patterns with shapes in the defect region window. This merging process can include rotating and mirroring the shapes in the defect region. The invention similarly transforms shapes in the defect region window into defect vectors by finding intersections between basis patterns and the shapes in the defect region. Then, the invention can easily find feature vectors that are similar to the defect vector using, for example, representative feature vectors from the index of feature vectors. Then, the similarities and differences between the defect vectors and the feature vectors can be analyzed.

    摘要翻译： 公开了一种定位集成电路系统缺陷的方法。 本发明首先进行电路设计的初步提取和索引处理，然后执行特征搜索。 当执行初步提取和索引处理时，本发明建立了用于电路设计的窗口网格，并且将窗体网格的每个窗口内的电路设计中的形状与基本图案合并。 本发明通过在窗口中找到基本图案和形状之间的交点来将每个窗口中的形状转换为特征向量。 然后，本发明聚集特征向量以产生特征向量的索引。 在执行提取和索引处理之后，本发明通过首先识别电路布局的缺陷区域窗口并且将基本模式与缺陷区域窗口中的形状类似地合并来执行特征搜索的处理。 该合并过程可以包括旋转和镜像缺陷区域中的形状。 本发明类似地通过在缺陷区域中找到基础图案和形状之间的交点来将缺陷区域窗口中的形状转换为缺陷向量。 然后，本发明可以使用例如来自特征向量的索引的代表性特征向量容易地找到与缺陷向量相似的特征向量。 然后，可以分析缺陷向量和特征向量之间的相似性和差异。

    Methodology to improve turnaround for integrated circuit design using geometrical hierarchy
    7.
    发明授权
    Methodology to improve turnaround for integrated circuit design using geometrical hierarchy 失效
    使用几何层次结构改善集成电路设计周转的方法

    公开(公告)号：US07669175B2

    公开(公告)日：2010-02-23

    申请号：US11747485

    申请日：2007-05-11

    申请人： James A. Culp ,  Maharaj Mukherjee ,  Timothy G. Dunham ,  Mark Lavin

    发明人： James A. Culp ,  Maharaj Mukherjee ,  Timothy G. Dunham ,  Mark Lavin

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5068 ,  G06F2217/12 ,  Y02P90/265

    摘要： A method of designing a layout for manufacturing an integrated circuit is provided, in which computationally intensive portions of the design process, such as simulation of an image transferred through a mask design, or simulation of electrical characteristics of a circuit, are performed more efficiently by only performing such computations on single instance of computational subunits that have an identical geometrical context. Thus, rather than performing such computations based on the functional layout, for which typical design process steps result in significant flattening of the functional hierarchy, and therefore increase the cost of computation, the invention performs simulations on computational subunits stored in a hierarchy based on geometrical context, which minimizes the cost of simulation. The resulting simulation results are subsequently assembled according to the functional layout.

    摘要翻译： 提供了一种设计用于制造集成电路的布局的方法，其中，通过设计处理的计算密集部分（诸如通过掩模设计传送的图像的模拟）或电路的电特性的模拟被更高效地执行 仅在具有相同几何上下文的计算子单元的单个实例上执行这样的计算。 因此，不是基于功能布局执行这样的计算，而是通过典型的设计过程步骤导致功能层次结构的显着平坦化，从而增加计算成本，本发明对基于几何的层次结构存储的计算子单元进行模拟 上下文，最大限度地降低了模拟成本。 随后根据功能布局组合得到的模拟结果。

    Method of IC fabrication, IC mask fabrication and program product therefor
    8.
    发明申请
    Method of IC fabrication, IC mask fabrication and program product therefor 失效
    IC制造方法，IC掩模制造及其程序产品

    公开(公告)号：US20050193363A1

    公开(公告)日：2005-09-01

    申请号：US11043482

    申请日：2005-01-26

    申请人： Puneet Gupta ,  Fook-Luen Heng ,  Mark Lavin

    发明人： Puneet Gupta ,  Fook-Luen Heng ,  Mark Lavin

    IPC分类号： G03F1/14 ,  G06F17/50

    CPC分类号： G03F1/36

    摘要： A method of forming integrated circuit (IC) chip shapes and a method and computer program product for converting an IC design to a mask, e.g., for standard cell design. Individual book/macro physical designs (layouts) are proximity corrected before unnesting and an outer proximity range is determined for each proximity corrected physical design. Shapes with a unique design (e.g., in boundary cells and unique instances of books) are tagged and the design is unnested. Only the unique shapes are proximity corrected in the unnested design, which may be used to make a mask for fabricating IC chips/wafers.

    摘要翻译： 一种形成集成电路（IC）芯片形状的方法以及用于将IC设计转换为掩模的方法和计算机程序产品，例如用于标准单元设计。 单独的书/宏物理设计（布局）在不需要之前进行邻近校正，并且为每个邻近校正的物理设计确定外部接近度范围。 具有独特设计的形状（例如，在边界单元格和图书的独特实例中）被标记，并且设计不被忽视。 只有独特的形状在未设计的设计中被接近校正，其可以用于制造用于制造IC芯片/晶片的掩模。

    Renesting interaction map into design for efficient long range calculations
    10.
    发明申请
    Renesting interaction map into design for efficient long range calculations 失效
    将交互图重新设计成有效的长距离计算

    公开(公告)号：US20050091634A1

    公开(公告)日：2005-04-28

    申请号：US10694339

    申请日：2003-10-27

    申请人： Gregg Gallatin ,  Emanuel Gofman ,  Kafai Lai ,  Mark Lavin ,  Maharaj Mukherjee ,  Dov Ramm ,  Alan Rosenbluth ,  Shlomo Shlafman

    发明人： Gregg Gallatin ,  Emanuel Gofman ,  Kafai Lai ,  Mark Lavin ,  Maharaj Mukherjee ,  Dov Ramm ,  Alan Rosenbluth ,  Shlomo Shlafman

    IPC分类号： G03F1/08 ,  G03F1/14 ,  G03F7/20 ,  G06F17/50 ,  H01L21/027 ,  H01L21/82

    CPC分类号： G03F1/36 ,  G03F1/68 ,  G06F17/5068

    摘要： Methods, and program storage devices, for performing model-based optical lithography corrections by partitioning a cell array layout, having a plurality of polygons thereon, into a plurality of cells covering the layout. This layout is representative of a desired design data hierarchy. A density map is then generated corresponding to interactions between the polygons and plurality of cells, and then the densities within each cell are convolved. An interaction map is formed using the convolved densities, followed by truncating the interaction map to form a map of truncated cells. Substantially identical groupings of the truncated cells are then segregated respectively into differing ones of a plurality of buckets, whereby each of these buckets comprise a single set of identical groupings of truncated cells. A hierarchal arrangement is generated using these buckets, and the desired design data hierarchy enforced using the hierarchal arrangement to ultimately correct for optical lithography.

    摘要翻译： 方法和程序存储装置，用于通过将具有多个多边形的单元阵列布局划分成覆盖布局的多个单元来执行基于模型的光学光刻校正。 该布局代表了所需的设计数据层次结构。 然后根据多边形与多个单元之间的相互作用产生密度图，然后卷积每个单元内的密度。 使用卷积密度形成交互图，然后截断交互图以形成截断单元格的图。 截短的细胞的基本相同的分组然后分别分离成多个桶中的不同的桶，由此这些桶中的每一个都包含一组相同的截断细胞组。 使用这些存储桶生成层次排列，并且使用层级排列来强制执行所需的设计数据层级，以最终校正光学光刻。