公开(公告)号：US08370691B1

公开(公告)日：2013-02-05

申请号：US13299507

申请日：2011-11-18

Applicant: Chan-Chi Jason Cheng ,  Qin Wei ,  Ting Yew

Inventor： Chan-Chi Jason Cheng ,  Qin Wei ,  Ting Yew

IPC: G01R31/28 ,  G11C29/00 ,  G06F11/00

CPC classification number: G01R31/31816 ,  G06F11/1004 ,  G11C11/41 ,  G11C29/52 ,  G11C2029/0401 ,  H03K19/17764

Abstract: In one embodiment, a programmable logic device (PLD) with configuration memory includes at least one configuration memory cell and soft error detection (SED) logic for checking for errors in data stored by the configuration memory. The SED logic calculates a present data value for the configuration memory for comparison with a pre-calculated data value. A fuse within the PLD is configurable in a first logic state to enable the SED logic to read from the configuration memory cell in calculating the present data value and configurable in a second logic state to prevent the SED logic from reading from the configuration memory cell in calculating the present data value. The SED logic may be tested for correct operation by writing data representing a soft error into the configuration memory cell and enabling the SED logic to read from the configuration memory cell in calculating the present data value.

Abstract translation: 在一个实施例中，具有配置存储器的可编程逻辑器件（PLD）包括至少一个配置存储器单元和用于检查由配置存储器存储的数据中的错误的软错误检测（SED）逻辑。 SED逻辑计算配置存储器的当前数据值，以便与预先计算的数据值进行比较。 PLD内的保险丝可配置成第一逻辑状态，以使得SED逻辑能够在计算当前数据值时从配置存储器单元读取并且可配置在第二逻辑状态以防止SED逻辑从配置存储器单元中读取 计算当前数据值。 可以通过将表示软错误的数据写入配置存储器单元来使SED逻辑被测试以进行正确的操作，并且在计算当前数据值时使SED逻辑能够从配置存储器单元读取。

公开(公告)号：US07576563B1

公开(公告)日：2009-08-18

申请号：US11671948

申请日：2007-02-06

Applicant: Qin Wei ,  Chan-Chi Jason Cheng ,  Brad Sharpe-Geisler ,  Ting Yew

Inventor： Qin Wei ,  Chan-Chi Jason Cheng ,  Brad Sharpe-Geisler ,  Ting Yew

IPC: H01L25/00

CPC classification number: H03K19/1774

Abstract: Systems and methods are disclosed herein to provide high fan-out signal routing. For example, in accordance with an embodiment of the present invention, a programmable logic device includes a plurality of logic blocks; an interconnect structure adapted to route signals among the logic blocks; and a secondary routing network adapted to route signals among the logic blocks. The secondary routing network may include a plurality of horizontal splines adapted to route signals within the programmable logic device; a plurality of vertical spline taps adapted to route signals within the programmable logic device; a plurality of common interface blocks adapted to route signals between the horizontal splines and the vertical spline taps; and a plurality of horizontal secondary branches adapted to route signals from the vertical spline taps to the logic blocks.

Abstract translation: 本文公开了提供高扇出信号路由的系统和方法。 例如，根据本发明的实施例，可编程逻辑器件包括多个逻辑块; 适于在逻辑块之间路由信号的互连结构; 以及适于在逻辑块之间路由信号的次路由网络。 辅助路由网络可以包括适于在可编程逻辑设备内路由信号的多个水平样条; 多个垂直样条抽头，适于在可编程逻辑器件内路由信号; 适于在水平样条和垂直样条抽头之间路由信号的多个公共接口块; 以及适于将来自垂直样条抽头的信号路由到逻辑块的多个水平次分支。

公开(公告)号：US07401280B1

公开(公告)日：2008-07-15

申请号：US11750790

申请日：2007-05-18

Applicant: Satwant Singh ,  Chi Nguyen ,  Ann Wu ,  Ting Yew

Inventor： Satwant Singh ,  Chi Nguyen ,  Ann Wu ,  Ting Yew

IPC: G01R31/28 ,  G06F11/00

CPC classification number: G11C29/42 ,  G01R31/318516 ,  G11C2029/0401 ,  G11C2029/0409 ,  H03K19/1776 ,  H03K19/17764

Abstract: In one embodiment, a programmable logic device is provided that includes a memory having memory cells, each memory cell operable to store either a configuration bit or a RAM bit; a masking circuit operable to mask a RAM bit by providing a masking value for the masked RAM bit; an error detection circuit operable to process the configuration bits during operation of the programmable logic device using an error detection algorithm, the error detection circuit calculating a signature that includes configuration bits and masking values; and a comparator operable to compare the signature calculated by the error detection circuit with a correct signature.

Abstract translation: 在一个实施例中，提供了包括具有存储器单元的存储器的可编程逻辑器件，每个存储器单元可操作以存储配置位或RAM位; 屏蔽电路，用于通过提供掩蔽的RAM位的掩蔽值来屏蔽RAM位; 误差检测电路，其可操作以使用错误检测算法在可编程逻辑器件的操作期间处理配置位，所述误差检测电路计算包括配置位和掩蔽值的签名; 以及比较器，用于将由误差检测电路计算的签名与正确的签名进行比较。

公开(公告)号：US07257750B1

公开(公告)日：2007-08-14

申请号：US11036630

申请日：2005-01-13

Applicant: Satwant Singh ,  Chi Nguyen ,  Ann Wu ,  Ting Yew

Inventor： Satwant Singh ,  Chi Nguyen ,  Ann Wu ,  Ting Yew

IPC: G01R31/28 ,  G06F11/00

CPC classification number: G11C29/42 ,  G01R31/318516 ,  G11C2029/0401 ,  G11C2029/0409 ,  H03K19/1776 ,  H03K19/17764

Abstract: In one embodiment, a programmable logic device is provided that includes a memory having memory cells, each memory cell operable to store either a configuration bit or a RAM bit; a masking circuit operable to mask a RAM bit by providing a masking value for the masked RAM bit; an error detection circuit operable to process the configuration bits during operation of the programmable logic device using an error detection algorithm, the error detection circuit calculating a signature that includes configuration bits and masking values; and a comparator operable to compare the signature calculated by the error detection circuit with a correct signature.

Abstract translation: 在一个实施例中，提供了包括具有存储器单元的存储器的可编程逻辑器件，每个存储器单元可操作以存储配置位或RAM位; 屏蔽电路，用于通过提供掩蔽的RAM位的掩蔽值来屏蔽RAM位; 误差检测电路，其可操作以使用错误检测算法在可编程逻辑器件的操作期间处理配置位，所述误差检测电路计算包括配置位和掩蔽值的签名; 以及比较器，用于将由误差检测电路计算的签名与正确的签名进行比较。

公开(公告)号：US08065574B1

公开(公告)日：2011-11-22

申请号：US11760411

申请日：2007-06-08

Applicant: Chan-Chi Jason Cheng ,  Qin Wei ,  Ting Yew

Inventor： Chan-Chi Jason Cheng ,  Qin Wei ,  Ting Yew

IPC: G01R31/28 ,  G11C29/00 ,  G06F11/00

CPC classification number: G01R31/31816 ,  G06F11/1004 ,  G11C11/41 ,  G11C29/52 ,  G11C2029/0401 ,  H03K19/17764

Abstract: A programmable logic device, in accordance with one embodiment, includes a plurality of configuration memory cells, wherein at least one configuration memory cell is adapted to function as random access memory. Read/write circuitry writes to and reads from a corresponding first port of the configuration memory cells, including reading from the at least one configuration memory cell adapted to function as random access memory. Soft error detection logic checks for an error in data values stored by the plurality of configuration memory cells, including the at least one configuration memory cell adapted to function as random access memory. The soft error detection logic, for example, may thus be tested by changing a data value stored in the at least one configuration memory cell.

Abstract translation: 根据一个实施例的可编程逻辑器件包括多个配置存储器单元，其中至少一个配置存储器单元适于用作随机存取存储器。 读/写电路写入和读取配置存储器单元的对应的第一端口，包括从适于用作随机存取存储器的至少一个配置存储器单元读取。 软错误检测逻辑检查由多个配置存储器单元存储的数据值中的错误，包括适于用作随机存取存储器的至少一个配置存储器单元。 因此，可以通过改变存储在至少一个配置存储单元中的数据值来测试软错误检测逻辑。