公开(公告)号：US08531882B2

公开(公告)日：2013-09-10

申请号：US13159696

申请日：2011-06-14

申请人： Tomofumi Fujimura ,  Yuui Shimizu

发明人： Tomofumi Fujimura ,  Yuui Shimizu

IPC分类号： G11C16/06

CPC分类号： G11C16/06 ,  G11C29/808

摘要： A memory includes stacking chips. The chip includes a pad commonly connected to the chips and receiving an enable signal that enables access to each chip. The chip includes a chip address memory that can store a chip address. The chip includes a determining part comparing a select address to the chip address for determining whether they match each other. The chip includes a control-signal setting part setting the control signal inputted to the chip itself to be valid or invalid depending on a determination made by the determining part. The chip includes a chip-address setting part determining whether the chip address is stored in the chip address memory depending on number of fail bits. The device includes a memory controller allocating respectively different ones of the chip addresses to the chips based on the number of fail bits.

摘要翻译： 存储器包括堆叠芯片。 该芯片包括通常连接到芯片的接收器，并且接收能够接入每个芯片的使能信号。 该芯片包括可存储芯片地址的芯片地址存储器。 芯片包括将选择地址与芯片地址进行比较以确定它们是否彼此匹配的确定部分。 该芯片包括控制信号设定部，其根据由判定部作出的判定，将输入到芯片本身的控制信号设定为有效或无效。 芯片包括芯片地址设定部，根据故障位的数量来判定芯片地址是否存储在芯片地址存储器中。 该装置包括一个存储器控制器，该存储器控制器基于故障位数来分别分配不同芯片地址到芯片。

公开(公告)号：US20090303790A1

公开(公告)日：2009-12-10

申请号：US12478172

申请日：2009-06-04

申请人： Tomofumi FUJIMURA ,  Kosuke YANAGIDAIRA

发明人： Tomofumi FUJIMURA ,  Kosuke YANAGIDAIRA

IPC分类号： G11C16/04

CPC分类号： G11C16/16 ,  G11C16/3409 ,  G11C16/344 ,  G11C16/3445

摘要： The present invention provides a semiconductor memory device that can minimize the widening of the threshold voltage distribution of cell transistors during a data erasing operation. The semiconductor memory device includes: a memory cell unit that is formed with nonvolatile memory cells connected in series, is divided into at least two groups each including one or more of the nonvolatile memory cells, and has one end connected to a source line and the other end connected to a bit line, word lines being connected to the gates of the nonvolatile memory cells, the voltages of the word lines being controlled to store data from the bit line or output stored data onto the bit line; and a voltage applying circuit that applies voltages to the word lines of the nonvolatile memory cells, applying a first voltage to the word lines of the nonvolatile memory cells of the group located closer to the bit line, and applying a second voltage to the word lines of the nonvolatile memory cells of the group located closer to the source line, with respect to the two adjacent groups of the memory cell unit, when a data erasing operation is performed to erase data stored in the nonvolatile memory cells forming the memory cell unit, the second voltage being higher than the first voltage.

摘要翻译： 本发明提供一种半导体存储器件，其能够在数据擦除操作期间最小化单元晶体管的阈值电压分布的加宽。 半导体存储器件包括：形成有串联连接的非易失性存储单元的存储单元单元，被分成至少两组，每组包括一个或多个非易失性存储单元，并且其一端连接到源极线，并且 另一端连接到位线，字线连接到非易失性存储单元的栅极，字线的电压被控制以存储来自位线的数据或将存储的数据输出到位线; 以及电压施加电路，对所述非易失性存储单元的字线施加电压，向位于所述位线附近的所述组的所述非易失性存储单元的字线施加第一电压，并向所述字线施加第二电压 相对于存储单元单元的两个相邻组而言，位于更靠近源极线的组的非易失性存储单元当执行数据擦除操作以擦除存储在形成存储单元单元的非易失性存储单元中的数据时， 第二电压高于第一电压。

公开(公告)号：US20110305086A1

公开(公告)日：2011-12-15

申请号：US13159696

申请日：2011-06-14

申请人： Tomofumi FUJIMURA ,  Yuui SHIMIZU

发明人： Tomofumi FUJIMURA ,  Yuui SHIMIZU

IPC分类号： G11C16/06

CPC分类号： G11C16/06 ,  G11C29/808

摘要： A memory includes stacking chips. The chip includes a pad commonly connected to the chips and receiving an enable signal that enables access to each chip. The chip includes a chip address memory that can store a chip address. The chip includes a determining part comparing a select address to the chip address for determining whether they match each other. The chip includes a control-signal setting part setting the control signal inputted to the chip itself to be valid or invalid depending on a determination made by the determining part. The chip includes a chip-address setting part determining whether the chip address is stored in the chip address memory depending on number of fail bits. The device includes a memory controller allocating respectively different ones of the chip addresses to the chips based on the number of fail bits.

摘要翻译： 存储器包括堆叠芯片。 该芯片包括通常连接到芯片的接收器，并且接收能够接入每个芯片的使能信号。 该芯片包括可存储芯片地址的芯片地址存储器。 芯片包括将选择地址与芯片地址进行比较以确定它们是否彼此匹配的确定部分。 该芯片包括控制信号设定部，其根据由判定部作出的判定，将输入到芯片本身的控制信号设定为有效或无效。 芯片包括芯片地址设定部，根据故障位的数量来判定芯片地址是否存储在芯片地址存储器中。 该装置包括一个存储器控制器，该存储器控制器基于故障位数来分别分配不同芯片地址到芯片。

公开(公告)号：US20120243331A1

公开(公告)日：2012-09-27

申请号：US13428497

申请日：2012-03-23

申请人： Tomofumi Fujimura ,  Yuya Suzuki

发明人： Tomofumi Fujimura ,  Yuya Suzuki

IPC分类号： G11C16/10

CPC分类号： G11C16/10 ,  G11C16/0483 ,  G11C16/3404

摘要： According to one embodiment, a semiconductor memory device includes a cell array, a voltage generator, and a controller. The memory cells are formed along rows and columns. The voltage generator generates a write voltage and a verify voltage. The voltage generator transfers a first voltage to the memory cell having a threshold voltage lower than the verify voltage. The voltage generator transfers a second voltage lower than the first voltage. The controller causes the voltage generator to transfer the verify voltage to the memory cell and to terminate a write operation. The controller performs the writing at least twice.

摘要翻译： 根据一个实施例，半导体存储器件包括单元阵列，电压发生器和控制器。 存储单元沿行和列形成。 电压发生器产生写入电压和验证电压。 电压发生器将第一电压传送到具有低于验证电压的阈值电压的存储单元。 电压发生器传送低于第一电压的第二电压。 控制器使得电压发生器将验证电压传送到存储器单元并终止写入操作。 控制器执行写入至少两次。

公开(公告)号：US07948796B2

公开(公告)日：2011-05-24

申请号：US12478172

申请日：2009-06-04

申请人： Tomofumi Fujimura ,  Kosuke Yanagidaira

发明人： Tomofumi Fujimura ,  Kosuke Yanagidaira

IPC分类号： G11C11/34

CPC分类号： G11C16/16 ,  G11C16/3409 ,  G11C16/344 ,  G11C16/3445

摘要： The present invention provides a semiconductor memory device that can minimize the widening of the threshold voltage distribution of cell transistors during a data erasing operation. The semiconductor memory device includes: a memory cell unit that is formed with nonvolatile memory cells connected in series, is divided into at least two groups each including one or more of the nonvolatile memory cells, and has one end connected to a source line and the other end connected to a bit line, word lines being connected to the gates of the nonvolatile memory cells, the voltages of the word lines being controlled to store data from the bit line or output stored data onto the bit line; and a voltage applying circuit that applies voltages to the word lines of the nonvolatile memory cells, applying a first voltage to the word lines of the nonvolatile memory cells of the group located closer to the bit line, and applying a second voltage to the word lines of the nonvolatile memory cells of the group located closer to the source line, with respect to the two adjacent groups of the memory cell unit, when a data erasing operation is performed to erase data stored in the nonvolatile memory cells forming the memory cell unit, the second voltage being higher than the first voltage.

摘要翻译： 本发明提供了一种半导体存储器件，其可以在数据擦除操作期间最小化单元晶体管的阈值电压分布的加宽。 半导体存储器件包括：形成有串联连接的非易失性存储单元的存储单元单元，被分成至少两组，每组包括一个或多个非易失性存储单元，并且其一端连接到源极线，并且 另一端连接到位线，字线连接到非易失性存储单元的栅极，字线的电压被控制以存储来自位线的数据或将存储的数据输出到位线上; 以及电压施加电路，对所述非易失性存储单元的字线施加电压，向位于所述位线附近的所述组的非易失性存储单元的字线施加第一电压，并向所述字线施加第二电压 相对于存储单元单元的两个相邻组而言，位于更靠近源极线的组的非易失性存储单元当执行数据擦除操作以擦除存储在形成存储单元单元的非易失性存储单元中的数据时， 第二电压高于第一电压。