公开(公告)号：US5889677A

公开(公告)日：1999-03-30

申请号：US574901

申请日：1995-12-19

申请人： Mitsuru Yasuda ,  Hiroyuki Sugiyama ,  Noriyuki Ito ,  Ryoichi Yamashita ,  Tadashi Konno ,  Yasunori Abe ,  Naomi Bizen ,  Terunobu Maruyama ,  Yoshiyuki Kato ,  Tomoyuki Isomura ,  Hiroshi Ikeda ,  Miki Takagi

发明人： Mitsuru Yasuda ,  Hiroyuki Sugiyama ,  Noriyuki Ito ,  Ryoichi Yamashita ,  Tadashi Konno ,  Yasunori Abe ,  Naomi Bizen ,  Terunobu Maruyama ,  Yoshiyuki Kato ,  Tomoyuki Isomura ,  Hiroshi Ikeda ,  Miki Takagi

IPC分类号： G06F17/50

CPC分类号： G06F17/5022

摘要： A circuit designing apparatus of an interactive type which enables a simplified and high-speed circuit design process while largely reducing a burden on a designer, having a speed analyzing unit for conducting a delay computation for each wiring path on a circuit to be designed and a display control unit for displaying a result of the delay computation by the speed analyzing unit on a display unit. When the speed analyzing unit conducts a delay computation, a delay value of each logic component forming the circuit that is an object of the design is set and altered according to a dullness of a signal waveform inputted to the logic component. The circuit designing apparatus of an interactive type may be applied to a system for conducting a circuit design of an integrated circuit such as an LSI or the like or a printed circuit board.

摘要翻译： 一种交互式的电路设计装置，其能够实现简化和高速电路设计过程，同时大大减轻设计者的负担，具有速度分析单元，用于对要设计的电路上的每个布线路径执行延迟计算，以及 显示控制单元，用于在显示单元上显示速度分析单元的延迟计算结果。 当速度分析单元进行延迟计算时，根据输入到逻辑部件的信号波形的钝度来设定和改变形成作为设计对象的电路的每个逻辑部件的延迟值。 交互式的电路设计装置可以应用于用于进行诸如LSI等的集成电路的电路设计的系统或印刷电路板。

公开(公告)号：US06240541B1

公开(公告)日：2001-05-29

申请号：US09227967

申请日：1999-01-11

申请人： Mitsuru Yasuda ,  Hiroyuki Sugiyama ,  Noriyuki Ito ,  Ryoichi Yamashita ,  Tadashi Konno ,  Yasunori Abe ,  Naomi Bizen ,  Terunobu Maruyama ,  Yoshiyuki Kato ,  Tomoyuki Isomura ,  Hiroshi Ikeda ,  Miki Takagi

发明人： Mitsuru Yasuda ,  Hiroyuki Sugiyama ,  Noriyuki Ito ,  Ryoichi Yamashita ,  Tadashi Konno ,  Yasunori Abe ,  Naomi Bizen ,  Terunobu Maruyama ,  Yoshiyuki Kato ,  Tomoyuki Isomura ,  Hiroshi Ikeda ,  Miki Takagi

IPC分类号： G06F1750

CPC分类号： G06F17/5022

摘要： A circuit designing apparatus of an interactive type which enables a simplified and highspeed circuit design process while largely reducing a burden on a designer, having a speed analyzing unit for conducting a delay computation for each wiring path on a circuit to be designed and a display control unit for displaying a result of the delay computation by the speed analyzing unit on a display unit. When the speed analyzing unit conducts a delay computation, a delay value of each logic component forming the circuit that is an object of the design is set and altered according to a dullness of a signal waveform inputted to the logic component. The circuit designing apparatus of an interactive type may be applied to a system for conducting a circuit design of an integrated circuit such as an LSI or the like or a printed circuit board.

摘要翻译： 一种交互式的电路设计装置，其能够实现简化和高速电路设计过程，同时大大减轻设计者的负担，具有用于对要设计的电路上的每个布线路径进行延迟计算的速度分析单元和显示控制 单元，用于在显示单元上显示速度分析单元的延迟计算结果。 当速度分析单元进行延迟计算时，根据输入到逻辑部件的信号波形的钝度来设定和改变形成作为设计对象的电路的每个逻辑部件的延迟值。 交互式的电路设计装置可以应用于用于进行诸如LSI等的集成电路的电路设计的系统或印刷电路板。

公开(公告)号：US09427717B2

公开(公告)日：2016-08-30

申请号：US13637042

申请日：2011-02-22

申请人： Hidetoshi Iwamatsu ,  Yoshiyuki Kato ,  Katsunobu Yoshimoto ,  Tsutomu Kurita ,  Masahiro Suzuki ,  Katsunori Ishii ,  Yoshiyuki Kihara

发明人： Hidetoshi Iwamatsu ,  Yoshiyuki Kato ,  Katsunobu Yoshimoto ,  Tsutomu Kurita ,  Masahiro Suzuki ,  Katsunori Ishii ,  Yoshiyuki Kihara

IPC分类号： B01J2/14 ,  B02C17/14 ,  B02C17/10 ,  B01J2/24

CPC分类号： B01J2/14 ,  B01J2/24 ,  B02C17/10 ,  B02C17/14

摘要： A powder granulation method affords greater operation efficiency and working efficiency and enhanced product recovery rate by preventing powder from being adhered to a container inner wall while suppressing variability in particle size of product to the utmost. A plurality of scrapers are disposed so as to abut or come close to the inner face of a bottomed cylindrical container that accommodates powder so that the powder in the container is granulated by causing an inner bottom surface of the container to rotate on a horizontal plane.

摘要翻译： 粉末造粒方法通过防止粉末粘附到容器内壁上，同时最大限度地抑制产品粒径的变化，从而提高了操作效率和加工效率，提高了产品回收率。 多个刮板被布置成邻接或靠近容纳粉末的有底圆筒形容器的内表面，使得容器中的粉末通过使容器的内底表面在水平面上旋转而造粒。

公开(公告)号：US08896699B2

公开(公告)日：2014-11-25

申请号：US13808985

申请日：2010-07-14

申请人： Takafumi Kasuga ,  Yoshiyuki Kato ,  Kiyotaka Kato ,  Akira Torii ,  Masaki Hamada ,  Eisuke Yonezawa

发明人： Takafumi Kasuga ,  Yoshiyuki Kato ,  Kiyotaka Kato ,  Akira Torii ,  Masaki Hamada ,  Eisuke Yonezawa

IPC分类号： H04N7/18

CPC分类号： H04N7/181

摘要： Disclosed is an image synthesis device including an area determining unit 3 for selecting a vehicle-mounted camera 1 used for generation of a bird's-eye view image viewed from an arbitrary point of view from vehicle-mounted cameras 1a to 1d mounted at different positions, and for determining an area corresponding to the bird's-eye view image in an image captured by the vehicle-mounted camera 1, and an input video signal control unit 4 for receiving image data about the area determined by the area determining unit 3, the image data being included in image data showing the image captured by the vehicle-mounted camera 1, to store the image data in an input frame buffer 5, in which an image processing device 6 generates a bird's-eye view image from the image data stored in the input frame buffer 5.

摘要翻译： 公开了一种图像合成装置，包括：区域确定单元3，用于从安装在不同位置的车载摄像机1a至1d的任意角度选择用于生成俯瞰图像的鸟瞰图像1的车载摄像机1， 并且用于确定由车载摄像机1捕获的图像中与鸟瞰图图像对应的区域，以及用于接收关于由区域确定单元3确定的区域的图像数据的输入视频信号控制单元4，图像 数据被包括在表示由车载摄像机1拍摄的图像的图像数据中，以将图像数据存储在输入帧缓冲器5中，其中图像处理装置6从存储在图像数据中的图像数据生成鸟瞰图图像 输入帧缓冲区5。

公开(公告)号：US08151226B2

公开(公告)日：2012-04-03

申请号：US11987811

申请日：2007-12-04

申请人： Yoshiyuki Kato ,  Hisashi Aoyama ,  Mitsuru Sato

发明人： Yoshiyuki Kato ,  Hisashi Aoyama ,  Mitsuru Sato

IPC分类号： G06F17/50

摘要： An FPGA-design-CAD interface unit retrieves pin assignment information created by an FPGA-designing CAD apparatus. An FPGA-pin-information managing unit manages the pin assignment information as FPGA pin information. A temporary-library creating unit creates a temporary component shape type library by using the FPGA pin information and outputs the temporary component shape type library in a form capable of being read by a package-designing CAD apparatus to a file.

公开(公告)号：US07995912B2

公开(公告)日：2011-08-09

申请号：US12720323

申请日：2010-03-09

申请人： Tomohiko Murakami ,  Yoshiyuki Kato ,  Takeshi Sato

发明人： Tomohiko Murakami ,  Yoshiyuki Kato ,  Takeshi Sato

IPC分类号： G03B15/05

CPC分类号： G03B15/06 ,  H04N5/2354

摘要： When the mode is set to a strobe consecutive shooting mode, an imaging apparatus sets the mode to a pixel addition drive mode for reading out image data using pixel addition drive, performs metering operation using preliminary flashing and calculates an appropriate amount of flashing on the basis of the metering operation. Next, the imaging apparatus judges whether or not it is possible to flash three times consecutively with the calculated amount of flashing. If it is judged that it is not possible to flash three times consecutively with the calculated amount of flashing, the imaging apparatus limits the amount of flashing to the largest amount of flashing within the range of amounts of flashing with which flashing of strobe light three times consecutively is possible, and performs strobe consecutive shooting with the limited amount of flashing.

摘要翻译： 当模式被设置为选通连续拍摄模式时，成像装置将该模式设置为使用像素相加驱动器读出图像数据的像素相加驱动模式，使用预先闪烁进行计量操作，并基于此计算适当的闪烁量 的计量操作。 接下来，成像装置判断是否可以用计算出的闪光量连续闪烁三次。 如果判断为不可能以计算出的闪光量连续三次闪烁，则成像装置将闪光量限制在闪光量的闪光量的最大闪光量的范围内，闪光灯闪烁三次 连续可能，并以有限量的闪烁进行频闪连续拍摄。

公开(公告)号：US07871471B2

公开(公告)日：2011-01-18

申请号：US12023316

申请日：2008-01-31

申请人： Yoshiyuki Kato

发明人： Yoshiyuki Kato

IPC分类号： B08B7/00 ,  H01L21/302

CPC分类号： H01L21/67069 ,  H01L21/67253 ,  H01L21/67288

摘要： It is intended to prevent an increase in the quantity of particles on a test-piece substrate having undergone processing executed at a low temperature equal to or lower than 0° C. In an inspection method adopted when inspecting the state inside a processing chamber by measuring the quantity of particles on a test-piece substrate, i.e., a test-piece wafer, the test-piece wafer W having undergone a specific type of test processing inside the processing chamber is carried out into a transfer chamber via a loadlock chamber after holding it in the loadlock chamber over a predetermined length of time while delivering a dried inert gas into the loadlock chamber. The predetermined length of time is set to a value at which the increase in the quantity of particles on the test-piece wafer can be kept down at least within an acceptable range.

摘要翻译： 旨在防止在等于或低于0℃的低温下进行的经过处理的试验片基板上的颗粒数量的增加。在通过测量检查处理室内的状态时所采用的检查方法 在试片基片即试片晶片上，在处理室内进行了特定类型的试验处理的试片晶片W在保持后通过负载锁定室进行转印室 将其在负载锁定室中预定长度的时间，同时将干燥的惰性气体输送到负载锁定室中。 预定的时间长度被设定为可以将试片晶片上的颗粒数量的增加保持在至少在可接受的范围内的值。

公开(公告)号：US07486836B2

公开(公告)日：2009-02-03

申请号：US11189303

申请日：2005-07-26

申请人： Yoshiyuki Kato

发明人： Yoshiyuki Kato

IPC分类号： G06K9/40 ,  G03F3/08

CPC分类号： H04N1/6027 ,  H04N1/4074

摘要： An image pickup device includes a histogram generation unit which generates a histogram representing a brightness distribution of digital image data (RAW data) acquired during picture taking and a table change unit which calculates an amount of correction with reference to a target brightness value based on the histogram and changes gradation correction information of a gamma lookup table in accordance with the amount of correction. A gamma correction unit corrects gradation of the image data using the changed gradation correction information to generate a taken image whose brightness is corrected in accordance with the target brightness value.

摘要翻译： 图像拾取装置包括：直方图生成单元，其生成表示在拍摄期间获取的数字图像数据（RAW数据）的亮度分布的直方图;以及表改变单元，其基于所述图像拾取装置参照目标亮度值计算校正量 直方图并根据校正量来改变伽马查找表的灰度校正信息。 伽马校正单元使用改变的灰度校正信息校正图像数据的灰度，以生成根据目标亮度值校正其亮度的拍摄图像。

公开(公告)号：US20080134124A1

公开(公告)日：2008-06-05

申请号：US11905129

申请日：2007-09-27

申请人： Yoshiyuki Kato ,  Hisashi Aoyama

发明人： Yoshiyuki Kato ,  Hisashi Aoyama

IPC分类号： G06F17/50

CPC分类号： G06F17/5054

摘要： An FPGA-information managing unit included in a circuit-designing CAD apparatus retrieves FPGA information, such as pin assignment information and attribute information, that is created by an FPGA-designing CAD apparatus. A library creating unit creates a symbol library by using the FPGA information. When creating a symbol library, if an FPGA subjected to create the symbol library is arranged in the circuit diagram, the library creating unit manages not to change a portion dividing and a pin layout of the existing symbol library arranged in the circuit diagram as much as possible. When arranging a symbol of the FPGA that a symbol library is newly created, a circuit-diagram reflecting unit arranges the symbol without changing the existing layout.

摘要翻译： 包括在电路设计CAD装置中的FPGA信息管理单元检索由FPGA设计CAD装置创建的诸如引脚分配信息和属性信息的FPGA信息。 库创建单元通过使用FPGA信息创建符号库。 当创建符号库时，如果经过创建符号库的FPGA被布置在电路图中，则库创建单元管理不将布置在电路图中的现有符号库的部分划分和引脚布局改变为 可能。 当重新创建符号库的FPGA的符号时，电路图反射单元排列符号而不改变现有的布局。

公开(公告)号：US20070133974A1

公开(公告)日：2007-06-14

申请号：US11635949

申请日：2006-12-08

申请人： Tomohiko Murakami ,  Yoshiyuki Kato ,  Takeshi Sato

发明人： Tomohiko Murakami ,  Yoshiyuki Kato ,  Takeshi Sato

IPC分类号： G03B15/03

CPC分类号： G03B15/06 ,  H04N5/2354

摘要： When the mode is set to a strobe consecutive shooting mode, an imaging apparatus sets the mode to a pixel addition drive mode for reading out image data using pixel addition drive (S7), performs metering operation using preliminary flashing (S8) and calculates an appropriate amount of flashing on the basis of the metering operation (S9). Next, the imaging apparatus judges whether or not it is possible to flash three times consecutively with the calculated amount of flashing (S10). If it is judged that it is not possible to flash three times consecutively with the calculated amount of flashing (NO in S10), the imaging apparatus limits the amount of flashing to the largest amount of flashing within the range of amounts of flashing with which flashing of strobe light three times consecutively is possible (S11), and performs strobe consecutive shooting with the limited amount of flashing (S13 to S17).

摘要翻译： 当模式被设置为选通连续拍摄模式时，成像装置将模式设置为使用像素相加驱动来读出图像数据的像素相加驱动模式（S7），使用预先闪烁进行计量操作（S8），并且计算 基于计量操作的适当量的闪烁（S 9）。 接下来，成像装置判断是否可以用计算出的闪光量连续闪烁三次（S10）。 如果判断为不能以计算出的闪光量连续闪烁三次（S10）中的“否”），则成像装置将闪光量限制在闪光量的最大量的范围内 可以连续三次闪烁闪光灯（S11），并以有限量的闪光进行选通连续拍摄（S13〜S17）。