公开(公告)号：US06301184B1

公开(公告)日：2001-10-09

申请号：US09480695

申请日：2000-01-11

申请人： Toshio Sasaki ,  Yoshihiko Yasu ,  Kazumasa Yanagisawa ,  Yuji Tanaka ,  Toshiaki Takahira ,  Yasuto Igarashi ,  Mariko Ohtsuka ,  Yasunobu Aoki

发明人： Toshio Sasaki ,  Yoshihiko Yasu ,  Kazumasa Yanagisawa ,  Yuji Tanaka ,  Toshiaki Takahira ,  Yasuto Igarashi ,  Mariko Ohtsuka ,  Yasunobu Aoki

IPC分类号： G11C800

CPC分类号： G11C11/4074 ,  G11C7/1045

摘要： A DRAM module is applied to the system LSI which is provided with a standby mode for suppressing the whole operation thereof and an operation standby mode which permits at least the DRAM module to operate but suppresses the operation of other circuits. The above-mentioned modes as well as a substrate bias control technology are applied to the CMOS system LSI that operates on a low voltage. The system LSI is controlled to hold or not to hold data, enabling a memory of a large capacity to be mounted and consuming a sufficiently decreased amount of electric power.

摘要翻译： 将DRAM模块应用于具有用于抑制其整体操作的待机模式的系统LSI和至少允许DRAM模块操作但抑制其它电路的操作的操作待机模式。 将上述模式以及衬底偏置控制技术应用于在低电压下工作的CMOS系统LSI。 控制系统LSI以保持或不保存数据，使得能够安装大容量的存储器并消耗足够的电力量。