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公开(公告)号:US07402473B2
公开(公告)日:2008-07-22
申请号:US11108827
申请日:2005-04-19
申请人: Norio Ishitsuka , Hideo Miura , Shuji Ikeda , Norio Suzuki , Yasushi Matsuda , Yasuko Yoshida , Hirohiko Yamamoto , Masamichi Kobayashi , Akira Takamatsu , Hirofumi Shimizu , Kazushi Fukuda , Shinichi Horibe , Toshio Nozoe
发明人: Norio Ishitsuka , Hideo Miura , Shuji Ikeda , Norio Suzuki , Yasushi Matsuda , Yasuko Yoshida , Hirohiko Yamamoto , Masamichi Kobayashi , Akira Takamatsu , Hirofumi Shimizu , Kazushi Fukuda , Shinichi Horibe , Toshio Nozoe
IPC分类号: H01L21/336 , H01L21/76
CPC分类号: H01L21/76232 , H01L21/76235 , H01L29/78
摘要: A process of producing a semiconductor device having a highly reliable groove isolation structure with a desired radius of curvature formed at the groove upper edge and without formation of any step. The device is produced by reducing the stress generation around the groove upper edge of an element isolation groove on a semiconductor substrate, thereby optimizing the shape of an element isolation groove and making the device finer and improving the device electric characteristics.
摘要翻译: 一种制造半导体器件的方法,该半导体器件具有高度可靠的凹槽隔离结构,其具有在凹槽上边缘处形成的所需曲率半径,并且不形成任何步骤。 通过减小半导体基板上的元件隔离槽的槽上缘周围的应力产生,从而优化元件隔离槽的形状并使器件更细,并提高器件电特性来制造器件。
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公开(公告)号:US06242323B1
公开(公告)日:2001-06-05
申请号:US09367524
申请日:1999-08-16
申请人: Norio Ishitsuka , Hideo Miura , Shuji Ikeda , Norio Suzuki , Yasushi Matsuda , Yasuko Yoshida , Hirohiko Yamamoto , Masamichi Kobayashi , Akira Takamatsu , Hirofumi Shimizu , Kazushi Fukuda , Shinichi Horibe , Toshio Nozoe
发明人: Norio Ishitsuka , Hideo Miura , Shuji Ikeda , Norio Suzuki , Yasushi Matsuda , Yasuko Yoshida , Hirohiko Yamamoto , Masamichi Kobayashi , Akira Takamatsu , Hirofumi Shimizu , Kazushi Fukuda , Shinichi Horibe , Toshio Nozoe
IPC分类号: H01L2176
CPC分类号: H01L21/76232 , H01L21/76235 , H01L29/78
摘要: A semiconductor device having a highly reliable groove isolation structure with a desired radius of curvature formed at the groove upper edge and without formation of any step, there is produced by reducing the stress generation around the groove upper edge of an element isolation groove on a semiconductor substrate, thereby optimizing the shape of an element isolation groove and making the device finer and improving the device electric characteristics.
摘要翻译: 一种半导体器件,其具有高度可靠的凹槽隔离结构,其具有在凹槽上边缘处形成的所需曲率半径,并且不形成任何步骤,通过减小半导体上的元件隔离槽的沟槽上边缘周围的应力产生而产生 从而优化元件隔离槽的形状并使器件更精细并提高器件的电气特性。
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公开(公告)号:US20050196935A1
公开(公告)日:2005-09-08
申请号:US11108827
申请日:2005-04-19
申请人: Norio Ishitsuka , Hideo Miura , Shuji Ikeda , Norio Suzuki , Yasushi Matsuda , Yasuko Yoshida , Hirohiko Yamamoto , Masamichi Kobayashi , Akira Takamatsu , Hirofumi Shimizu , Kazushi Fukuda , Shinichi Horibe , Toshio Nozoe
发明人: Norio Ishitsuka , Hideo Miura , Shuji Ikeda , Norio Suzuki , Yasushi Matsuda , Yasuko Yoshida , Hirohiko Yamamoto , Masamichi Kobayashi , Akira Takamatsu , Hirofumi Shimizu , Kazushi Fukuda , Shinichi Horibe , Toshio Nozoe
IPC分类号: H01L21/31 , H01L21/76 , H01L21/762
CPC分类号: H01L21/76232 , H01L21/76235 , H01L29/78
摘要: A process of producing a semiconductor device having a highly reliable groove isolation structure with a desired radius of curvature formed at the groove upper edge and without formation of any step. The device is produced by reducing the stress generation around the groove upper edge of an element isolation groove on a semiconductor substrate, thereby optimizing the shape of an element isolation groove and making the device finer and improving the device electric characteristics.
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公开(公告)号:US06881646B2
公开(公告)日:2005-04-19
申请号:US10392916
申请日:2003-03-21
申请人: Norio Ishitsuka , Hideo Miura , Shuji Ikeda , Norio Suzuki , Yasushi Matsuda , Yasuko Yoshida , Hirohiko Yamamoto , Masamichi Kobayashi , Akira Takamatsu , Hirofumi Shimizu , Kazushi Fukuda , Shinichi Horibe , Toshio Nozoe
发明人: Norio Ishitsuka , Hideo Miura , Shuji Ikeda , Norio Suzuki , Yasushi Matsuda , Yasuko Yoshida , Hirohiko Yamamoto , Masamichi Kobayashi , Akira Takamatsu , Hirofumi Shimizu , Kazushi Fukuda , Shinichi Horibe , Toshio Nozoe
IPC分类号: H01L21/31 , H01L21/76 , H01L21/762
CPC分类号: H01L21/76232 , H01L21/76235 , H01L29/78
摘要: A process of producing a semiconductor device having a highly reliable groove isolation structure with a desired radius of curvature formed at the groove upper edge and without formation of any step. The device is produced by reducing the stress generation around the groove upper edge of an element isolation groove on a semiconductor substrate, thereby optimizing the shape of an element isolation groove and making the device finer and improving the device electric characteristics.
摘要翻译: 一种制造半导体器件的方法,该半导体器件具有高度可靠的凹槽隔离结构,其具有在凹槽上边缘处形成的所需曲率半径,并且不形成任何步骤。 通过减小半导体衬底上的元件隔离槽的槽上边缘周围的应力产生,从而优化元件隔离槽的形状并使器件更精细并提高器件电气特性来制造器件。
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公开(公告)号:US6057241A
公开(公告)日:2000-05-02
申请号:US66757
申请日:1998-04-27
申请人: Yasushi Matsuda , Hideo Miura , Hirohiko Yamamoto , Masamichi Kobayashi , Shuji Ikeda , Akira Takamatsu , Norio Suzuki , Hirofumi Shimizu , Yasuko Yoshida , Kazushi Fukuda , Shinichi Horibe , Toshio Nozoe
发明人: Yasushi Matsuda , Hideo Miura , Hirohiko Yamamoto , Masamichi Kobayashi , Shuji Ikeda , Akira Takamatsu , Norio Suzuki , Hirofumi Shimizu , Yasuko Yoshida , Kazushi Fukuda , Shinichi Horibe , Toshio Nozoe
IPC分类号: H01L21/76 , H01L21/477
CPC分类号: H01L21/477 , H01L21/76
摘要: A silicon oxide film 2 which is exposed from a side wall of a groove 4a is etched to displace the silicon oxide film 2 backward toward an active region. The displacement amount is set to be equal to or more than a film thickness (Tr) of a silicon oxide film 5 to be formed on an inner wall of the groove 4a in a later thermal oxidation step and equal to or less than twice the film thickness (Tr) thereof. A shoulder portion of the groove 4a can be rounded by a low-temperature heat treatment at 1000.degree. C. or less, by controlling a heat treatment period such that the film thickness (Tr) of the silicon oxide film 5 is more than the film thickness (Tp) of the silicon oxide film 2 and equal to or less than three times the film thickness (Tr) thereof (Tp
摘要翻译: 蚀刻从槽4a的侧壁露出的氧化硅膜2,使氧化硅膜2朝向有源区域反向移动。 位移量被设定为等于或大于在随后的热氧化步骤中形成在凹槽4a的内壁上的氧化硅膜5的膜厚度(Tr),并且等于或小于两倍的膜 厚度(Tr)。 通过控制热处理时间使得氧化硅膜5的膜厚(Tr)大于膜的厚度(Tr),可以通过在1000℃以下的低温热处理使槽4a的肩部成圆形 氧化硅膜2的厚度(Tp)等于或小于其厚度(Tr)的三倍(Tp
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公开(公告)号:US06559027B2
公开(公告)日:2003-05-06
申请号:US09845338
申请日:2001-05-01
申请人: Norio Ishitsuka , Hideo Miura , Shuji Ikeda , Norio Suzuki , Yasushi Matsuda , Yasuko Yoshida , Hirohiko Yamamoto , Masamichi Kobayashi , Akira Takamatsu , Hirofumi Shimizu , Kazushi Fukuda , Shinichi Horibe , Toshio Nozoe
发明人: Norio Ishitsuka , Hideo Miura , Shuji Ikeda , Norio Suzuki , Yasushi Matsuda , Yasuko Yoshida , Hirohiko Yamamoto , Masamichi Kobayashi , Akira Takamatsu , Hirofumi Shimizu , Kazushi Fukuda , Shinichi Horibe , Toshio Nozoe
IPC分类号: H01L2176
CPC分类号: H01L21/76232 , H01L21/76235 , H01L29/78
摘要: A semiconductor device having a highly reliable groove isolation structure with a desired radius of curvature formed at the groove upper edge and without formation of any step, there is produced by reducing the stress generation around the groove upper edge of an element isolation groove on a semiconductor substrate, thereby optimizing the shape of an element isolation groove and making the device finer and improving the device electric characteristics.
摘要翻译: 一种半导体器件,其具有高度可靠的凹槽隔离结构,其具有在凹槽上边缘处形成的所需曲率半径,并且不形成任何步骤,通过减小半导体上的元件隔离槽的沟槽上边缘周围的应力产生而产生 从而优化元件隔离槽的形状并使器件更精细并提高器件的电气特性。
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