公开(公告)号：US20050196935A1

公开(公告)日：2005-09-08

申请号：US11108827

申请日：2005-04-19

申请人： Norio Ishitsuka ,  Hideo Miura ,  Shuji Ikeda ,  Norio Suzuki ,  Yasushi Matsuda ,  Yasuko Yoshida ,  Hirohiko Yamamoto ,  Masamichi Kobayashi ,  Akira Takamatsu ,  Hirofumi Shimizu ,  Kazushi Fukuda ,  Shinichi Horibe ,  Toshio Nozoe

发明人： Norio Ishitsuka ,  Hideo Miura ,  Shuji Ikeda ,  Norio Suzuki ,  Yasushi Matsuda ,  Yasuko Yoshida ,  Hirohiko Yamamoto ,  Masamichi Kobayashi ,  Akira Takamatsu ,  Hirofumi Shimizu ,  Kazushi Fukuda ,  Shinichi Horibe ,  Toshio Nozoe

IPC分类号： H01L21/31 ,  H01L21/76 ,  H01L21/762

CPC分类号： H01L21/76232 ,  H01L21/76235 ,  H01L29/78

摘要： A process of producing a semiconductor device having a highly reliable groove isolation structure with a desired radius of curvature formed at the groove upper edge and without formation of any step. The device is produced by reducing the stress generation around the groove upper edge of an element isolation groove on a semiconductor substrate, thereby optimizing the shape of an element isolation groove and making the device finer and improving the device electric characteristics.

公开(公告)号：US06881646B2

公开(公告)日：2005-04-19

申请号：US10392916

申请日：2003-03-21

申请人： Norio Ishitsuka ,  Hideo Miura ,  Shuji Ikeda ,  Norio Suzuki ,  Yasushi Matsuda ,  Yasuko Yoshida ,  Hirohiko Yamamoto ,  Masamichi Kobayashi ,  Akira Takamatsu ,  Hirofumi Shimizu ,  Kazushi Fukuda ,  Shinichi Horibe ,  Toshio Nozoe

发明人： Norio Ishitsuka ,  Hideo Miura ,  Shuji Ikeda ,  Norio Suzuki ,  Yasushi Matsuda ,  Yasuko Yoshida ,  Hirohiko Yamamoto ,  Masamichi Kobayashi ,  Akira Takamatsu ,  Hirofumi Shimizu ,  Kazushi Fukuda ,  Shinichi Horibe ,  Toshio Nozoe

IPC分类号： H01L21/31 ,  H01L21/76 ,  H01L21/762

CPC分类号： H01L21/76232 ,  H01L21/76235 ,  H01L29/78

摘要： A process of producing a semiconductor device having a highly reliable groove isolation structure with a desired radius of curvature formed at the groove upper edge and without formation of any step. The device is produced by reducing the stress generation around the groove upper edge of an element isolation groove on a semiconductor substrate, thereby optimizing the shape of an element isolation groove and making the device finer and improving the device electric characteristics.

摘要翻译： 一种制造半导体器件的方法，该半导体器件具有高度可靠的凹槽隔离结构，其具有在凹槽上边缘处形成的所需曲率半径，并且不形成任何步骤。 通过减小半导体衬底上的元件隔离槽的槽上边缘周围的应力产生，从而优化元件隔离槽的形状并使器件更精细并提高器件电气特性来制造器件。

公开(公告)号：US07402473B2

公开(公告)日：2008-07-22

申请号：US11108827

申请日：2005-04-19

申请人： Norio Ishitsuka ,  Hideo Miura ,  Shuji Ikeda ,  Norio Suzuki ,  Yasushi Matsuda ,  Yasuko Yoshida ,  Hirohiko Yamamoto ,  Masamichi Kobayashi ,  Akira Takamatsu ,  Hirofumi Shimizu ,  Kazushi Fukuda ,  Shinichi Horibe ,  Toshio Nozoe

发明人： Norio Ishitsuka ,  Hideo Miura ,  Shuji Ikeda ,  Norio Suzuki ,  Yasushi Matsuda ,  Yasuko Yoshida ,  Hirohiko Yamamoto ,  Masamichi Kobayashi ,  Akira Takamatsu ,  Hirofumi Shimizu ,  Kazushi Fukuda ,  Shinichi Horibe ,  Toshio Nozoe

IPC分类号： H01L21/336 ,  H01L21/76

CPC分类号： H01L21/76232 ,  H01L21/76235 ,  H01L29/78

摘要： A process of producing a semiconductor device having a highly reliable groove isolation structure with a desired radius of curvature formed at the groove upper edge and without formation of any step. The device is produced by reducing the stress generation around the groove upper edge of an element isolation groove on a semiconductor substrate, thereby optimizing the shape of an element isolation groove and making the device finer and improving the device electric characteristics.

摘要翻译： 一种制造半导体器件的方法，该半导体器件具有高度可靠的凹槽隔离结构，其具有在凹槽上边缘处形成的所需曲率半径，并且不形成任何步骤。 通过减小半导体基板上的元件隔离槽的槽上缘周围的应力产生，从而优化元件隔离槽的形状并使器件更细，并提高器件电特性来制造器件。

公开(公告)号：US06242323B1

公开(公告)日：2001-06-05

申请号：US09367524

申请日：1999-08-16

申请人： Norio Ishitsuka ,  Hideo Miura ,  Shuji Ikeda ,  Norio Suzuki ,  Yasushi Matsuda ,  Yasuko Yoshida ,  Hirohiko Yamamoto ,  Masamichi Kobayashi ,  Akira Takamatsu ,  Hirofumi Shimizu ,  Kazushi Fukuda ,  Shinichi Horibe ,  Toshio Nozoe

发明人： Norio Ishitsuka ,  Hideo Miura ,  Shuji Ikeda ,  Norio Suzuki ,  Yasushi Matsuda ,  Yasuko Yoshida ,  Hirohiko Yamamoto ,  Masamichi Kobayashi ,  Akira Takamatsu ,  Hirofumi Shimizu ,  Kazushi Fukuda ,  Shinichi Horibe ,  Toshio Nozoe

IPC分类号： H01L2176

CPC分类号： H01L21/76232 ,  H01L21/76235 ,  H01L29/78

摘要： A semiconductor device having a highly reliable groove isolation structure with a desired radius of curvature formed at the groove upper edge and without formation of any step, there is produced by reducing the stress generation around the groove upper edge of an element isolation groove on a semiconductor substrate, thereby optimizing the shape of an element isolation groove and making the device finer and improving the device electric characteristics.

摘要翻译： 一种半导体器件，其具有高度可靠的凹槽隔离结构，其具有在凹槽上边缘处形成的所需曲率半径，并且不形成任何步骤，通过减小半导体上的元件隔离槽的沟槽上边缘周围的应力产生而产生 从而优化元件隔离槽的形状并使器件更精细并提高器件的电气特性。

公开(公告)号：US06559027B2

公开(公告)日：2003-05-06

申请号：US09845338

申请日：2001-05-01

申请人： Norio Ishitsuka ,  Hideo Miura ,  Shuji Ikeda ,  Norio Suzuki ,  Yasushi Matsuda ,  Yasuko Yoshida ,  Hirohiko Yamamoto ,  Masamichi Kobayashi ,  Akira Takamatsu ,  Hirofumi Shimizu ,  Kazushi Fukuda ,  Shinichi Horibe ,  Toshio Nozoe

发明人： Norio Ishitsuka ,  Hideo Miura ,  Shuji Ikeda ,  Norio Suzuki ,  Yasushi Matsuda ,  Yasuko Yoshida ,  Hirohiko Yamamoto ,  Masamichi Kobayashi ,  Akira Takamatsu ,  Hirofumi Shimizu ,  Kazushi Fukuda ,  Shinichi Horibe ,  Toshio Nozoe

IPC分类号： H01L2176

CPC分类号： H01L21/76232 ,  H01L21/76235 ,  H01L29/78

摘要： A semiconductor device having a highly reliable groove isolation structure with a desired radius of curvature formed at the groove upper edge and without formation of any step, there is produced by reducing the stress generation around the groove upper edge of an element isolation groove on a semiconductor substrate, thereby optimizing the shape of an element isolation groove and making the device finer and improving the device electric characteristics.

摘要翻译： 一种半导体器件，其具有高度可靠的凹槽隔离结构，其具有在凹槽上边缘处形成的所需曲率半径，并且不形成任何步骤，通过减小半导体上的元件隔离槽的沟槽上边缘周围的应力产生而产生 从而优化元件隔离槽的形状并使器件更精细并提高器件的电气特性。

公开(公告)号：US6057241A

公开(公告)日：2000-05-02

申请号：US66757

申请日：1998-04-27

申请人： Yasushi Matsuda ,  Hideo Miura ,  Hirohiko Yamamoto ,  Masamichi Kobayashi ,  Shuji Ikeda ,  Akira Takamatsu ,  Norio Suzuki ,  Hirofumi Shimizu ,  Yasuko Yoshida ,  Kazushi Fukuda ,  Shinichi Horibe ,  Toshio Nozoe

发明人： Yasushi Matsuda ,  Hideo Miura ,  Hirohiko Yamamoto ,  Masamichi Kobayashi ,  Shuji Ikeda ,  Akira Takamatsu ,  Norio Suzuki ,  Hirofumi Shimizu ,  Yasuko Yoshida ,  Kazushi Fukuda ,  Shinichi Horibe ,  Toshio Nozoe

IPC分类号： H01L21/76 ,  H01L21/477

CPC分类号： H01L21/477 ,  H01L21/76

摘要： A silicon oxide film 2 which is exposed from a side wall of a groove 4a is etched to displace the silicon oxide film 2 backward toward an active region. The displacement amount is set to be equal to or more than a film thickness (Tr) of a silicon oxide film 5 to be formed on an inner wall of the groove 4a in a later thermal oxidation step and equal to or less than twice the film thickness (Tr) thereof. A shoulder portion of the groove 4a can be rounded by a low-temperature heat treatment at 1000.degree. C. or less, by controlling a heat treatment period such that the film thickness (Tr) of the silicon oxide film 5 is more than the film thickness (Tp) of the silicon oxide film 2 and equal to or less than three times the film thickness (Tr) thereof (Tp

摘要翻译： 蚀刻从槽4a的侧壁露出的氧化硅膜2，使氧化硅膜2朝向有源区域反向移动。 位移量被设定为等于或大于在随后的热氧化步骤中形成在凹槽4a的内壁上的氧化硅膜5的膜厚度（Tr），并且等于或小于两倍的膜 厚度（Tr）。 通过控制热处理时间使得氧化硅膜5的膜厚（Tr）大于膜的厚度（Tr），可以通过在1000℃以下的低温热处理使槽4a的肩部成圆形 氧化硅膜2的厚度（Tp）等于或小于其厚度（Tr）的三倍（Tp

公开(公告)号：US5780328A

公开(公告)日：1998-07-14

申请号：US835197

申请日：1997-04-07

申请人： Kazushi Fukuda ,  Yasuko Yoshida ,  Yutaka Hoshino ,  Naotaka Hashimoto ,  Kyoichiro Asayama ,  Yuuki Koide ,  Keiichi Yoshizumi ,  Eri Okamoto ,  Satoru Haga ,  Shuji Ikeda

发明人： Kazushi Fukuda ,  Yasuko Yoshida ,  Yutaka Hoshino ,  Naotaka Hashimoto ,  Kyoichiro Asayama ,  Yuuki Koide ,  Keiichi Yoshizumi ,  Eri Okamoto ,  Satoru Haga ,  Shuji Ikeda

IPC分类号： H01L27/088 ,  H01L21/8234 ,  H01L21/8238 ,  H01L21/8239 ,  H01L21/8244 ,  H01L27/11 ,  H01L21/336

CPC分类号： H01L21/823814 ,  H01L21/823871 ,  H01L27/1052 ,  H01L27/11 ,  H01L27/1104

摘要： When the source and drain regions (an n.sup.- type semiconductor region and an n.sup.+ type semiconductor region) of a complementary MISFET and a p-type semiconductor region for use as a punch-through stopper are formed in a p-type well in a substrate having a p- and an n-type well, p-type impurities for the punch-through stopper are suppressed from being supplied to the feeding portion (an n.sup.+ type semiconductor region) of the n-type well.

摘要翻译： 当在衬底中的p型阱中形成用作穿通阻挡层的互补MISFET和p型半导体区域的源区和漏区（n型半导体区和n +型半导体区） 具有p型和n型阱时，抑制了穿通止动件的p型杂质被供给到n型阱的馈电部（n +型半导体区）。

公开(公告)号：US5880497A

公开(公告)日：1999-03-09

申请号：US592235

申请日：1996-01-26

申请人： Shuji Ikeda ,  Koichi Imato ,  Kazuo Yoshizaki ,  Kohji Yamasaki ,  Soichiro Hashiba ,  Keiichi Yoshizumi ,  Yasuko Yoshida ,  Kousuke Okuyama ,  Mitsugu Oshima ,  Kazushi Tomita ,  Tsuyoshi Tabata ,  Kazushi Fukuda ,  Junichi Takano ,  Toshiaki Yamanaka ,  Chiemi Hashimoto ,  Motoko Kawashima ,  Fumiyuki Kanai ,  Takashi Hashimoto

发明人： Shuji Ikeda ,  Koichi Imato ,  Kazuo Yoshizaki ,  Kohji Yamasaki ,  Soichiro Hashiba ,  Keiichi Yoshizumi ,  Yasuko Yoshida ,  Kousuke Okuyama ,  Mitsugu Oshima ,  Kazushi Tomita ,  Tsuyoshi Tabata ,  Kazushi Fukuda ,  Junichi Takano ,  Toshiaki Yamanaka ,  Chiemi Hashimoto ,  Motoko Kawashima ,  Fumiyuki Kanai ,  Takashi Hashimoto

IPC分类号： H01L27/11

CPC分类号： H01L27/1108 ,  Y10S257/903 ,  Y10S257/904

摘要： A SRAM having its memory cell constructed to include transfer MISFETs to be controlled by word lines and a flip-flop circuit having driver MISFETs and load MISFETs. Plate electrodes of large area fixed on predetermined power source lines are arranged over the load MISFETs such that the plate electrodes over the offset region of the load MISFETs are formed with an opening. A silicon nitride film having a thickness permeable to hydrogen but not to humidity is formed over the transfer MISFETs and the driver MISFETs formed over the main surface of a semiconductor substrate and the load MISFETs formed of a polycrystalline silicon film deposited on the driver MISFETs.

摘要翻译： 其存储单元被构造成包括由字线控制的转移MISFET和具有驱动器MISFET和负载MISFET的触发器电路的SRAM。 固定在预定电源线上的大面积平板电极布置在负载MISFET上，使得负载MISFET的偏移区域上的平板电极形成开口。 在半导体衬底的主表面上形成的转移MISFET和驱动器MISFET上形成具有可渗透氢而不湿度的氮化硅膜，以及沉积在驱动器MISFET上的多晶硅膜形成的负载MISFET。

公开(公告)号：US5508540A

公开(公告)日：1996-04-16

申请号：US190596

申请日：1994-02-02

申请人： Shuji Ikeda ,  Koichi Imato ,  Kazuo Yoshizaki ,  Kohji Yamasaki ,  Soichiro Hashiba ,  Keiichi Yoshizumi ,  Yasuko Yoshida ,  Kousuke Okuyama ,  Mitsugu Oshima ,  Kazushi Tomita ,  Tsuyoshi Tabata ,  Kazushi Fukuda ,  Junichi Takano ,  Toshiaki Yamanaka ,  Chiemi Hashimoto ,  Motoko Kawashima ,  Fumiyuki Kanai ,  Takashi Hashimoto

发明人： Shuji Ikeda ,  Koichi Imato ,  Kazuo Yoshizaki ,  Kohji Yamasaki ,  Soichiro Hashiba ,  Keiichi Yoshizumi ,  Yasuko Yoshida ,  Kousuke Okuyama ,  Mitsugu Oshima ,  Kazushi Tomita ,  Tsuyoshi Tabata ,  Kazushi Fukuda ,  Junichi Takano ,  Toshiaki Yamanaka ,  Chiemi Hashimoto ,  Motoko Kawashima ,  Fumiyuki Kanai ,  Takashi Hashimoto

IPC分类号： H01L27/11 ,  H01L27/108 ,  H01L29/04 ,  H01L29/76

CPC分类号： H01L27/1108 ,  Y10S257/903 ,  Y10S257/904

摘要： A SRAM having its memory cell constructed to include transfer MISFETs to be controlled by word lines and a flip-flop circuit having driver MISFETs and load MISFETs. Plate electrodes of large area fixed on predetermined power source lines are arranged over the load MISFETs such that the plate electrodes over the offset region of the load MISFETs are formed with an opening. A silicon nitride film having a thickness permeable to hydrogen but not to humidity is formed over the transfer MISFETs and the driver MISFETs formed over the main surface of a semiconductor substrate and the load MISFETs formed of a polycrystalline silicon film deposited on the driver MISFETs.

摘要翻译： 其存储单元被构造成包括由字线控制的转移MISFET和具有驱动器MISFET和负载MISFET的触发器电路的SRAM。 固定在预定电源线上的大面积平板电极布置在负载MISFET上，使得负载MISFET的偏移区域上的平板电极形成开口。 在半导体衬底的主表面上形成的转移MISFET和驱动器MISFET上形成具有可渗透氢而不湿度的氮化硅膜，以及沉积在驱动器MISFET上的多晶硅膜形成的负载MISFET。

公开(公告)号：US5444012A

公开(公告)日：1995-08-22

申请号：US278073

申请日：1994-07-20

申请人： Keiichi Yoshizumi ,  Kazushi Fukuda ,  Seiichi Ariga ,  Shuji Ikeda ,  Makoto Saeki ,  Kiyoshi Nagai ,  Soichiro Hashiba ,  Shinji Nishihara ,  Fumiyuki Kanai

发明人： Keiichi Yoshizumi ,  Kazushi Fukuda ,  Seiichi Ariga ,  Shuji Ikeda ,  Makoto Saeki ,  Kiyoshi Nagai ,  Soichiro Hashiba ,  Shinji Nishihara ,  Fumiyuki Kanai

IPC分类号： H01L21/66 ,  H01L21/768 ,  H01L21/82 ,  H01L21/822 ,  H01L21/8244 ,  H01L23/522 ,  H01L23/525 ,  H01L27/04 ,  H01L21/70 ,  H01L27/00

CPC分类号： H01L27/11 ,  H01L23/5256 ,  H01L2924/0002 ,  Y10S148/055

摘要： In depositing a silicon oxide film which constitutes part of a final passivation film onto a bonding pad formed on an interlayer insulating film, the silicon oxide depositing step is divided in two stages, and after the first deposition, the bonding pad is once exposed by etching, then the second deposition is performed, whereby the silicon oxide film which has thus been deposited in two stages is formed over a fuse element formed under the interlayer insulating film, while on the bonding pad is formed only the silicon oxide film deposited in the second stage. As a result, at the time of etching polyimide resin, silicon nitride film and silicon oxide film successively to expose the bonding pad, there remains a sufficient thickness of insulating film between the bottom of an aperture which is formed at the same time and the fuse element. Thereafter, an electrical test is conducted while applying a probe to the bonding pad and, where required, the fuse element located under the aperture is cut.

摘要翻译： 在将构成最终钝化膜的一部分的氧化硅膜沉积到形成在层间绝缘膜上的接合焊盘上的情况下，将氧化硅沉积步骤分成两个阶段，在第一次沉积之后，通过蚀刻将接合焊盘一次曝光 ，然后进行第二沉积，由此形成在层间绝缘膜下面的熔丝元件上形成两级沉积的氧化硅膜，而在焊盘上仅形成沉积在第二层中的氧化硅膜 阶段。 结果，在蚀刻聚酰亚胺树脂，氮化硅膜和氧化硅膜时，连续地露出接合焊盘，在同时形成的孔的底部和熔丝之间保持足够的绝缘膜厚度 元件。 此后，在将探针施加到接合焊盘的同时进行电气测试，并且如果需要，则切割位于孔下方的熔丝元件。