公开(公告)号：US08042078B2

公开(公告)日：2011-10-18

申请号：US12416232

申请日：2009-04-01

申请人： Viresh Paruthi ,  Travis W. Pouarz ,  Mark A. Williams

发明人： Viresh Paruthi ,  Travis W. Pouarz ,  Mark A. Williams

IPC分类号： G06F9/455 ,  G06F17/50

CPC分类号： G06F17/504

摘要： A method, a system and a computer program product for re-using verification results associated with a circuit design to eliminate a formal verification re-run associated with a subsequent verification of the circuit design. A Verification Data Re-use (VDR) utility initiates the creation of a first netlist data structure and a first set of target signatures for the circuit design. The VDR utility initiates an initial functional verification run of the circuit design and stores the results of the verification run. When a subsequent verification of the initial design is initiated, the VDR utility compares the first set of target signatures with a second set of target signatures for the subsequent verification run. A match of target signatures indicates that corresponding design targets have an identical functionality and the VDR utility re-uses verification results from the initial verification run to eliminate an extensive formal verification re-run for the circuit design.

摘要翻译： 一种用于重新使用与电路设计相关联的验证结果的方法，系统和计算机程序产品，以消除与电路设计的后续验证相关​​联的形式验证重新运行。 验证数据重用（VDR）实用程序启动为电路设计创建第一个网表数据结构和第一组目标签名。 VDR实用程序启动电路设计的初始功能验证运行，并存储验证运行的结果。 当启动初始设计的后续验证时，VDR实用程序将第一组目标签名与第二组目标签名进行比较，以用于后续验证运行。 目标签名的匹配表明相应的设计目标具有相同的功能，VDR实用程序重新使用初始验证运行的验证结果，以消除电路设计的广泛的正式验证重新运行。

公开(公告)号：US07546561B2

公开(公告)日：2009-06-09

申请号：US11420264

申请日：2006-05-25

申请人： Travis W. Pouarz ,  Viresh Paruthi

发明人： Travis W. Pouarz ,  Viresh Paruthi

IPC分类号： G06F17/50

CPC分类号： G01R31/318544

摘要： A system and method for determining scan chain correspondence including defining a reference scan chain having reference latches and a reference constraint, each of the reference latches having a reference latch logic cone, the reference constraint having a reference constraint logic cone and being associated with one of the reference latches; defining an implementation scan chain having implementation latches and an implementation constraint, each of the implementation latches having an implementation latch logic cone, the implementation constraint having an implementation constraint logic cone and being associated with one of the implementation latches; matching known corresponding scan points between the reference scan chain and the implementation scan chain; and determining scan chain functional correspondence between the reference latches and the implementation latches from the reference latch logic cones with any associated reference constraint logic cone and the implementation latch logic cones with any associated implementation constraint logic cone.

摘要翻译： 一种用于确定扫描链对应的系统和方法，包括定义具有参考锁存器和参考约束的参考扫描链，每个参考锁存器具有参考锁存逻辑锥，所述参考约束具有参考约束逻辑锥并且与 参考锁存器; 定义具有实现锁存器和实现约束的实现扫描链，每个实现锁存器具有实现锁存逻辑锥，所述实现约束具有实现约束逻辑锥并且与实现锁存器之一相关联; 在参考扫描链和实施扫描链之间匹配已知的相应扫描点; 以及从参考锁存逻辑锥与任何相关联的参考约束逻辑锥确定参考锁存器和实现锁存器之间的扫描链功能对应关系，并且实现锁存逻辑与任何相关联的实现约束逻辑锥形结合。

公开(公告)号：US20070277068A1

公开(公告)日：2007-11-29

申请号：US11420264

申请日：2006-05-25

申请人： Travis W. Pouarz ,  Viresh Paruthi

发明人： Travis W. Pouarz ,  Viresh Paruthi

IPC分类号： G01R31/28

CPC分类号： G01R31/318544

摘要： A system and method for determining scan chain correspondence including defining a reference scan chain having reference latches and a reference constraint, each of the reference latches having a reference latch logic cone, the reference constraint having a reference constraint logic cone and being associated with one of the reference latches; defining an implementation scan chain having implementation latches and an implementation constraint, each of the implementation latches having an implementation latch logic cone, the implementation constraint having an implementation constraint logic cone and being associated with one of the implementation latches; matching known corresponding scan points between the reference scan chain and the implementation scan chain; and determining scan chain functional correspondence between the reference latches and the implementation latches from the reference latch logic cones with any associated reference constraint logic cone and the implementation latch logic cones with any associated implementation constraint logic cone.

摘要翻译： 一种用于确定扫描链对应的系统和方法，包括定义具有参考锁存器和参考约束的参考扫描链，每个参考锁存器具有参考锁存逻辑锥，所述参考约束具有参考约束逻辑锥并且与 参考锁存器; 定义具有实现锁存器和实现约束的实现扫描链，每个实现锁存器具有实现锁存逻辑锥，所述实现约束具有实现约束逻辑锥并且与实现锁存器之一相关联; 在参考扫描链和实施扫描链之间匹配已知的相应扫描点; 以及从参考锁存逻辑锥与任何相关联的参考约束逻辑锥确定参考锁存器和实现锁存器之间的扫描链功能对应关系，并且实现锁存逻辑与任何相关联的实现约束逻辑锥形结合。

公开(公告)号：US20100257494A1

公开(公告)日：2010-10-07

申请号：US12416232

申请日：2009-04-01

申请人： Travis W. Pouarz ,  Viresh Paruthi ,  Mark A. Williams

发明人： Travis W. Pouarz ,  Viresh Paruthi ,  Mark A. Williams

IPC分类号： G06F17/50

CPC分类号： G06F17/504

摘要： A method, a system and a computer program product for re-using verification results associated with a circuit design to eliminate a formal verification re-run associated with a subsequent verification of the circuit design. A Verification Data Re-use (VDR) utility initiates the creation of a first netlist data structure and a first set of target signatures for the circuit design. The VDR utility initiates an initial functional verification run of the circuit design and stores the results of the verification run. When a subsequent verification of the initial design is initiated, the VDR utility compares the first set of target signatures with a second set of target signatures for the subsequent verification run. A match of target signatures indicates that corresponding design targets have an identical functionality and the VDR utility re-uses verification results from the initial verification run to eliminate an extensive formal verification

摘要翻译： 一种用于重新使用与电路设计相关联的验证结果的方法，系统和计算机程序产品，以消除与电路设计的后续验证相关​​联的形式验证重新运行。 验证数据重用（VDR）实用程序启动为电路设计创建第一个网表数据结构和第一组目标签名。 VDR实用程序启动电路设计的初始功能验证运行，并存储验证运行的结果。 当启动初始设计的后续验证时，VDR实用程序将第一组目标签名与第二组目标签名进行比较，以用于后续验证运行。 目标签名的匹配表明相应的设计目标具有相同的功能，VDR实用程序重新使用初始验证运行的验证结果，以消除广泛的形式验证

公开(公告)号：US20090013206A1

公开(公告)日：2009-01-08

申请号：US11772908

申请日：2007-07-03

申请人： Lawrence D. Curley ,  John M. Isakson ,  Arjen Mets ,  Travis W. Pouarz ,  Thomas E. Rosser ,  Kristen M. Tucker

发明人： Lawrence D. Curley ,  John M. Isakson ,  Arjen Mets ,  Travis W. Pouarz ,  Thomas E. Rosser ,  Kristen M. Tucker

IPC分类号： G06F1/14

CPC分类号： G06F17/505 ,  G06F2217/62

摘要： A method, system, and computer program product are provided for achieving timing closure in a clocked logic circuit. For each local clock buffer in a set of local clock buffers, a logic synthesis tool determines a clock control signal input from a set of clock control signal inputs that will drive a clock control signal to the local clock buffer at a target frequency such that a first timing constraint may be met. The operation performed by the logic synthesis tool forms a determined clock control signal input. Responsive to the logic synthesis tool determining the determined clock control signal input, the logic synthesis tool couples the local clock buffer to the determined clock control signal input that drives the clock control signal to the local clock buffer at the target frequency to achieve timing closure in the clocked logic circuit.

摘要翻译： 提供了一种方法，系统和计算机程序产品，用于实现时钟逻辑电路中的定时关闭。 对于一组本地时钟缓冲器中的每个本地时钟缓冲器，逻辑综合工具确定从一组时钟控制信号输入端输入的时钟控制信号，该时钟控制信号输入将以目标频率将时钟控制信号驱动到本地时钟缓冲器， 可以满足第一时间约束。 由逻辑综合工具执行的操作形成确定的时钟控制信号输入。 响应于确定所确定的时钟控制信号输入的逻辑综合工具，逻辑综合工具将本地时钟缓冲器耦合到所确定的时钟控制信号输入端，该时钟控制信号输入以目标频率驱动时钟控制信号到本地时钟缓冲器，以实现定时闭合 时钟逻辑电路。

公开(公告)号：US07979732B2

公开(公告)日：2011-07-12

申请号：US11772908

申请日：2007-07-03

申请人： Lawrence D. Curley ,  John M. Isakson ,  Arjen Mets ,  Travis W. Pouarz ,  Thomas E. Rosser ,  Kristen M. Tucker

发明人： Lawrence D. Curley ,  John M. Isakson ,  Arjen Mets ,  Travis W. Pouarz ,  Thomas E. Rosser ,  Kristen M. Tucker

IPC分类号： G06F1/12 ,  G06F1/14

CPC分类号： G06F17/505 ,  G06F2217/62

摘要： A method, system, and computer program product are provided for achieving timing closure in a clocked logic circuit. For each local clock buffer in a set of local clock buffers, a logic synthesis tool determines a clock control signal input from a set of clock control signal inputs that will drive a clock control signal to the local clock buffer at a target frequency such that a first timing constraint may be met. The operation performed by the logic synthesis tool forms a determined clock control signal input. Responsive to the logic synthesis tool determining the determined clock control signal input, the logic synthesis tool couples the local clock buffer to the determined clock control signal input that drives the clock control signal to the local clock buffer at the target frequency to achieve timing closure in the clocked logic circuit.

摘要翻译： 提供了一种方法，系统和计算机程序产品，用于实现时钟逻辑电路中的定时关闭。 对于一组本地时钟缓冲器中的每个本地时钟缓冲器，逻辑综合工具确定从一组时钟控制信号输入端输入的时钟控制信号，该时钟控制信号输入将以目标频率将时钟控制信号驱动到本地时钟缓冲器， 可以满足第一时间约束。 由逻辑综合工具执行的操作形成确定的时钟控制信号输入。 响应于确定所确定的时钟控制信号输入的逻辑综合工具，逻辑综合工具将本地时钟缓冲器耦合到所确定的时钟控制信号输入端，该时钟控制信号输入以目标频率驱动时钟控制信号到本地时钟缓冲器，以实现定时闭合 时钟逻辑电路。