公开(公告)号：US20100257494A1

公开(公告)日：2010-10-07

申请号：US12416232

申请日：2009-04-01

申请人： Travis W. Pouarz ,  Viresh Paruthi ,  Mark A. Williams

发明人： Travis W. Pouarz ,  Viresh Paruthi ,  Mark A. Williams

IPC分类号： G06F17/50

CPC分类号： G06F17/504

摘要： A method, a system and a computer program product for re-using verification results associated with a circuit design to eliminate a formal verification re-run associated with a subsequent verification of the circuit design. A Verification Data Re-use (VDR) utility initiates the creation of a first netlist data structure and a first set of target signatures for the circuit design. The VDR utility initiates an initial functional verification run of the circuit design and stores the results of the verification run. When a subsequent verification of the initial design is initiated, the VDR utility compares the first set of target signatures with a second set of target signatures for the subsequent verification run. A match of target signatures indicates that corresponding design targets have an identical functionality and the VDR utility re-uses verification results from the initial verification run to eliminate an extensive formal verification

摘要翻译： 一种用于重新使用与电路设计相关联的验证结果的方法，系统和计算机程序产品，以消除与电路设计的后续验证相关​​联的形式验证重新运行。 验证数据重用（VDR）实用程序启动为电路设计创建第一个网表数据结构和第一组目标签名。 VDR实用程序启动电路设计的初始功能验证运行，并存储验证运行的结果。 当启动初始设计的后续验证时，VDR实用程序将第一组目标签名与第二组目标签名进行比较，以用于后续验证运行。 目标签名的匹配表明相应的设计目标具有相同的功能，VDR实用程序重新使用初始验证运行的验证结果，以消除广泛的形式验证

公开(公告)号：US07546561B2

公开(公告)日：2009-06-09

申请号：US11420264

申请日：2006-05-25

申请人： Travis W. Pouarz ,  Viresh Paruthi

发明人： Travis W. Pouarz ,  Viresh Paruthi

IPC分类号： G06F17/50

CPC分类号： G01R31/318544

摘要： A system and method for determining scan chain correspondence including defining a reference scan chain having reference latches and a reference constraint, each of the reference latches having a reference latch logic cone, the reference constraint having a reference constraint logic cone and being associated with one of the reference latches; defining an implementation scan chain having implementation latches and an implementation constraint, each of the implementation latches having an implementation latch logic cone, the implementation constraint having an implementation constraint logic cone and being associated with one of the implementation latches; matching known corresponding scan points between the reference scan chain and the implementation scan chain; and determining scan chain functional correspondence between the reference latches and the implementation latches from the reference latch logic cones with any associated reference constraint logic cone and the implementation latch logic cones with any associated implementation constraint logic cone.

摘要翻译： 一种用于确定扫描链对应的系统和方法，包括定义具有参考锁存器和参考约束的参考扫描链，每个参考锁存器具有参考锁存逻辑锥，所述参考约束具有参考约束逻辑锥并且与 参考锁存器; 定义具有实现锁存器和实现约束的实现扫描链，每个实现锁存器具有实现锁存逻辑锥，所述实现约束具有实现约束逻辑锥并且与实现锁存器之一相关联; 在参考扫描链和实施扫描链之间匹配已知的相应扫描点; 以及从参考锁存逻辑锥与任何相关联的参考约束逻辑锥确定参考锁存器和实现锁存器之间的扫描链功能对应关系，并且实现锁存逻辑与任何相关联的实现约束逻辑锥形结合。

公开(公告)号：US20070277068A1

公开(公告)日：2007-11-29

申请号：US11420264

申请日：2006-05-25

申请人： Travis W. Pouarz ,  Viresh Paruthi

发明人： Travis W. Pouarz ,  Viresh Paruthi

IPC分类号： G01R31/28

CPC分类号： G01R31/318544

摘要： A system and method for determining scan chain correspondence including defining a reference scan chain having reference latches and a reference constraint, each of the reference latches having a reference latch logic cone, the reference constraint having a reference constraint logic cone and being associated with one of the reference latches; defining an implementation scan chain having implementation latches and an implementation constraint, each of the implementation latches having an implementation latch logic cone, the implementation constraint having an implementation constraint logic cone and being associated with one of the implementation latches; matching known corresponding scan points between the reference scan chain and the implementation scan chain; and determining scan chain functional correspondence between the reference latches and the implementation latches from the reference latch logic cones with any associated reference constraint logic cone and the implementation latch logic cones with any associated implementation constraint logic cone.

摘要翻译： 一种用于确定扫描链对应的系统和方法，包括定义具有参考锁存器和参考约束的参考扫描链，每个参考锁存器具有参考锁存逻辑锥，所述参考约束具有参考约束逻辑锥并且与 参考锁存器; 定义具有实现锁存器和实现约束的实现扫描链，每个实现锁存器具有实现锁存逻辑锥，所述实现约束具有实现约束逻辑锥并且与实现锁存器之一相关联; 在参考扫描链和实施扫描链之间匹配已知的相应扫描点; 以及从参考锁存逻辑锥与任何相关联的参考约束逻辑锥确定参考锁存器和实现锁存器之间的扫描链功能对应关系，并且实现锁存逻辑与任何相关联的实现约束逻辑锥形结合。

公开(公告)号：US08042078B2

公开(公告)日：2011-10-18

申请号：US12416232

申请日：2009-04-01

申请人： Viresh Paruthi ,  Travis W. Pouarz ,  Mark A. Williams

发明人： Viresh Paruthi ,  Travis W. Pouarz ,  Mark A. Williams

IPC分类号： G06F9/455 ,  G06F17/50

CPC分类号： G06F17/504

摘要： A method, a system and a computer program product for re-using verification results associated with a circuit design to eliminate a formal verification re-run associated with a subsequent verification of the circuit design. A Verification Data Re-use (VDR) utility initiates the creation of a first netlist data structure and a first set of target signatures for the circuit design. The VDR utility initiates an initial functional verification run of the circuit design and stores the results of the verification run. When a subsequent verification of the initial design is initiated, the VDR utility compares the first set of target signatures with a second set of target signatures for the subsequent verification run. A match of target signatures indicates that corresponding design targets have an identical functionality and the VDR utility re-uses verification results from the initial verification run to eliminate an extensive formal verification re-run for the circuit design.

摘要翻译： 一种用于重新使用与电路设计相关联的验证结果的方法，系统和计算机程序产品，以消除与电路设计的后续验证相关​​联的形式验证重新运行。 验证数据重用（VDR）实用程序启动为电路设计创建第一个网表数据结构和第一组目标签名。 VDR实用程序启动电路设计的初始功能验证运行，并存储验证运行的结果。 当启动初始设计的后续验证时，VDR实用程序将第一组目标签名与第二组目标签名进行比较，以用于后续验证运行。 目标签名的匹配表明相应的设计目标具有相同的功能，VDR实用程序重新使用初始验证运行的验证结果，以消除电路设计的广泛的正式验证重新运行。

公开(公告)号：US09063807B2

公开(公告)日：2015-06-23

申请号：US13594253

申请日：2012-08-24

申请人： Krishnan Kunjunny Kailas ,  Brian Chan Monwai ,  Viresh Paruthi

发明人： Krishnan Kunjunny Kailas ,  Brian Chan Monwai ,  Viresh Paruthi

IPC分类号： G06F7/58 ,  G06F13/14

CPC分类号： G06F7/58 ,  G06F13/14

摘要： A random number generator includes a fairness checker and correction module that ensures that a complete random sequence within a predetermined period of time will be output by the random number generator.

摘要翻译： 随机数生成器包括公平校验器和校正模块，其确保在随机数发生器内将在预定时间段内的完整随机序列输出。

公开(公告)号：US08756543B2

公开(公告)日：2014-06-17

申请号：US13097171

申请日：2011-04-29

申请人： Viresh Paruthi ,  Peter Anthony Sandon ,  Jun Sawada

发明人： Viresh Paruthi ,  Peter Anthony Sandon ,  Jun Sawada

IPC分类号： G06F9/455 ,  G06F17/50

CPC分类号： G06F17/504 ,  G06F9/4498 ,  G06F17/5022

摘要： A method, system, and computer program product for verification of a state transition machine (STM) are provided in the illustrative embodiments. The STM representing the operation of a circuit configured to perform a computation is received. A segment of the STM is selected from a set of segments of the STM. A set of properties of the segment is determined. The set of properties is translated into a hardware description to form a translation. The segment is verified by verifying whether all relationships between a pre-condition and a post condition in the translation hold true for any set of inputs and any initial state of a hardware design under test. A verification result for the segment is generated. Verification results for each segment in the set of segments are combined to generate a verification result for the STM.

摘要翻译： 在说明性实施例中提供了用于验证状态转换机（STM）的方法，系统和计算机程序产品。 接收表示被配置为执行计算的电路的操作的STM。 从STM的一组段中选择STM的一段。 确定该段的一组属性。 该属性集被翻译成硬件描述以形成一个翻译。 通过验证翻译中的前提条件和后期条件之间的所有关系是否适用于任何一组输入以及所测试的硬件设计的任何初始状态来验证该段。 生成段的验证结果。 组合段中每个段的验证结果，以生成STM的验证结果。

公开(公告)号：US08397189B2

公开(公告)日：2013-03-12

申请号：US13097193

申请日：2011-04-29

申请人： Viresh Paruthi ,  Peter Anthony Sandon ,  Jun Sawada

发明人： Viresh Paruthi ,  Peter Anthony Sandon ,  Jun Sawada

IPC分类号： G06F9/455

CPC分类号： G06F17/504

摘要： A method, system, and computer program product for improved model checking for verification of a state transition machine (STM) are provided. A hardware design under test and a property to be verified are received. A level (k) of induction proof needed for the verification is determined. A circuit representation of the property using the hardware design under test for k base cases is configured for checking that the circuit representation holds true for the property for each of the k base cases, and for testing an induction without hypothesis by testing whether the property holds true after k clock cycles starting from a randomized state, where induction without hypothesis is performed by omitting a test whether the property holds true for the next cycle after the property holds for k successive cycles. The induction proof of the property using the hardware design under test by induction without hypothesis is produced.

摘要翻译： 提供了一种用于改进状态转换机（STM）验证的模型检查的方法，系统和计算机程序产品。 收到被测试的硬件设计和待验证的属性。 确定验证所需的感应等级（k）。 配置用于k个基本情况的使用被测硬件设计的属性的电路表示被配置用于检查电路表示对于每个k个基本情况的属性是否成立，以及通过测试属性是否保持来测试没有假设的感应 在从随机化状态开始的k个时钟周期之后为真，其中通过省略在k个连续循环的该属性成立后的下一个周期的属性是否成立的情况下执行无假设的诱导。 产生使用通过没有假设的感应的被测硬件设计的属性的感应证明。

公开(公告)号：US20120096204A1

公开(公告)日：2012-04-19

申请号：US12906495

申请日：2010-10-18

申请人： Gadiel Auerbach ,  Fady Copty ,  David J. Levitt ,  Viresh Paruthi

发明人： Gadiel Auerbach ,  Fady Copty ,  David J. Levitt ,  Viresh Paruthi

IPC分类号： G06F13/37

CPC分类号： G06F13/364

摘要： A mechanism is provide for formally verifying random priority-based arbiters. A determination is made as to whether a random priority-based arbiter is blocking one of a set of output ports or a set of input ports. Responsive to the first predetermined time period expiring before the processor determines whether the random priority-based arbiter is blocking, a determination is made as to whether the random priority-based arbiter is blocking one of the set of output ports or the set of input ports within a second predetermined time period using the random seed and at least one of property strengthening or underapproximation. Responsive to the processor determining that the random priority-based arbiter satisfies a non-blocking specification such that not one of the set of output ports or the set of input ports is blocked within the second predetermined time period, the random priority-based arbiter is validated as satisfying the non-blocking specification.

摘要翻译： 提供了一种正式验证随机优先级仲裁器的机制。 确定随机优先级仲裁器是否阻塞一组输出端口或一组输入端口中的一个。 响应于在处理器确定基于随机优先级的仲裁器是否阻塞之前到期的第一预定时间段，确定基于随机优先级的仲裁器是否阻塞该组输出端口或输入端口组中的一个 在第二预定时间段内使用所述随机种子和性能加强或不足近似中的至少一种。 响应于所述处理器确定所述基于随机优先级的仲裁器满足非阻塞规范，使得所述一组输出端口或所述一组输入端口中的一个在所述第二预定时间段内被阻止，所述基于随机优先级的仲裁器是 验证满足非阻塞规范。

公开(公告)号：US08141048B2

公开(公告)日：2012-03-20

申请号：US11677652

申请日：2007-02-22

申请人： Jason R. Baumgartner ,  Ali S. El-Zein ,  Viresh Paruthi ,  Fadi A. Zaraket

发明人： Jason R. Baumgartner ,  Ali S. El-Zein ,  Viresh Paruthi ,  Fadi A. Zaraket

IPC分类号： G06F9/44 ,  G06F9/455

CPC分类号： G06F8/43

摘要： A method of verifying a software system includes receiving a description of a software system described utilizing a high-level modeling language, and responsive thereto, parsing the description and constructing an abstract syntax graph. The abstract syntax graph is transformed into a sequential logic representation of the software system. The sequential logic representation is formed by reference to a Hardware Description Language (HDL) library. Then, the sequential logic representation is transformed into a gate-level sequential logic representation. Following the transforming, the software system is verified based upon the gate-level sequential logic representation. Following verification, results of verification of the software system are output.

摘要翻译： 验证软件系统的方法包括接收使用高级建模语言描述的软件系统的描述，并且响应于此，解析描述并构造抽象语法图。 抽象语法图被转换成软件系统的顺序逻辑表示。 通过参考硬件描述语言（HDL）库形成顺序逻辑表示。 然后，顺序逻辑表示被转换成门级顺序逻辑表示。 在变换之后，基于门级顺序逻辑表示验证软件系统。 验证后，输出软件系统的验证结果。

公开(公告)号：US08015523B2

公开(公告)日：2011-09-06

申请号：US12392278

申请日：2009-02-25

申请人： Jason R. Baumgartner ,  Robert L. Kanzelman ,  Hari Mony ,  Viresh Paruthi

发明人： Jason R. Baumgartner ,  Robert L. Kanzelman ,  Hari Mony ,  Viresh Paruthi

IPC分类号： G06F17/50 ,  G06F9/455

CPC分类号： G06F17/505 ,  G06F17/504

摘要： Methods and systems are provided for sequential netlist reduction through trace-containment for a circuitry design netlist by first identifying a cut of the netlist and enumerating a set of mismatch traces. Perform time-bounded unfolding of a cofactored version of the cut to reflect the sequential cofactor for a specific input i and temporal uncorrelation constraints for the set of inputs ‘J’. Determine whether there is trace containment by performing equivalence checking with respect to the cut of the netlist under temporal uncorrelation constraints for the set of inputs ‘J’. In response to detecting trace containment, simplify the netlist by merging the input ‘i’ to a constant.

摘要翻译： 提供方法和系统，用于通过电路设计网表的跟踪容纳来顺序的网表减少，首先识别网表的剪切并列举一组不匹配的跟踪。 执行切片的辅助版本的时间限制展开，以反映特定输入i的顺序辅因子和输入集合J'的时间非相关约束。 通过对输入集合J'的时间不相关约束执行相对于网表的切分的等价性检查来确定是否存在跟踪容纳。 响应检测跟踪容纳，通过将输入'i'合并为常数来简化网表。