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公开(公告)号：US09034756B2
公开(公告)日：2015-05-19
申请号：US13559107
申请日：2012-07-26
IPC分类号： H01L21/44 , H01L21/768 , H01L23/522 , H01L23/532
CPC分类号： H01L23/5226 , H01L21/76802 , H01L21/7682 , H01L21/76831 , H01L21/76834 , H01L21/76885 , H01L23/5222 , H01L23/528 , H01L23/53233 , H01L23/53238 , H01L23/5329 , H01L23/53295 , H01L2924/00 , H01L2924/0002
摘要： A copper alloy layer is blanket deposited over a low k dielectric layer and in via openings within the low k dielectric layer. The blanket deposited layer is then anisotropically etch to form horizontal interconnects. The interconnects are annealed to form a metal oxide barrier lining. A second low k dielectric layer is then depositing over the horizontal interconnects. Air gaps can be formed between adjacent interconnects to lower parasitic capacitance therebetween.
摘要翻译： 铜合金层被覆盖在低k电介质层和低k电介质层内的通孔中。 然后将覆盖层沉积层各向异性地蚀刻以形成水平互连。 将互连件退火以形成金属氧化物屏障衬里。 然后第二低k电介质层在水平互连上沉积。 可以在相邻互连之间形成气隙，以降低它们之间的寄生电容。
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公开(公告)号：US20140065816A1
公开(公告)日：2014-03-06
申请号：US13600504
申请日：2012-08-31
申请人： Tsung-Jung Tsai , Hsin-Chieh Yao , Chien-Hua Huang , Chung-Ju Lee
发明人： Tsung-Jung Tsai , Hsin-Chieh Yao , Chien-Hua Huang , Chung-Ju Lee
IPC分类号： H01L21/768
CPC分类号： H01L21/76885 , H01L21/76831
摘要： Among other things, one or more techniques for forming a low k dielectric around a metal line during an integrated circuit (IC) fabrication process are provided. In an embodiment, a metal line is formed prior to forming a surrounding low k dielectric layer around the metal line. In an embodiment, the metal line is formed by filling a trench space in a skeleton layer with metal. In this embodiment, the skeleton layer is removed to form a dielectric space in a different location than the trench space. The dielectric space is then filled with a low k dielectric material to form a surrounding low k dielectric layer around the metal line. In this manner, damage to the surrounding low k dielectric layer, that would otherwise occur if the surrounding low k dielectric layer was etched, for example, is mitigated.
摘要翻译： 其中，提供了在集成电路（IC）制造过程中用于在金属线周围形成低k电介质的一种或多种技术。 在一个实施例中，在围绕金属线形成周围的低k电介质层之前形成金属线。 在一个实施例中，通过用金属填充骨架层中的沟槽空间来形成金属线。 在该实施例中，除去骨架层以在与沟槽空间不同的位置形成电介质空间。 然后用低k电介质材料填充电介质空间，以在金属线周围形成周围的低k电介质层。 以这种方式，例如，如果周围的低k电介质层被蚀刻，则会损坏周围的低k电介质层，否则会被破坏。
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公开(公告)号：US06975071B2
公开(公告)日：2005-12-13
申请号：US10634671
申请日：2003-08-06
申请人： Tsung-Jung Tsai
发明人： Tsung-Jung Tsai
IPC分类号： H05B41/288 , B60Q1/02 , H05B41/16
CPC分类号： H05B41/2882
摘要： A voltage booster of a headlight is connected between a power supply and a headlight and comprises a high frequency circuit, a voltage boost circuit, a rectified circuit, and a high frequency control circuit. The voltage booster comprises an over current sensing circuit connected in front of the headlight and a relay connected between the headlight and the power supply end. When the voltage booster is over circuit, power will supply to the headlight directly. By the voltage booster, the illumination of the headlight is increased and voltage can be stabilized.
摘要翻译： 大灯的升压器连接在电源和前照灯之间，并且包括高频电路，升压电路，整流电路和高频控制电路。 升压器包括连接在大灯前面的过电流检测电路和连接在前灯和电源端之间的继电器。 当升压器过电压时，电源将直接供给大灯。 通过升压器，大灯的照明增加，电压可以稳定。
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公开(公告)号：US20140027908A1
公开(公告)日：2014-01-30
申请号：US13559107
申请日：2012-07-26
IPC分类号： H01L21/768 , H01L23/535
CPC分类号： H01L23/5226 , H01L21/76802 , H01L21/7682 , H01L21/76831 , H01L21/76834 , H01L21/76885 , H01L23/5222 , H01L23/528 , H01L23/53233 , H01L23/53238 , H01L23/5329 , H01L23/53295 , H01L2924/00 , H01L2924/0002
摘要： A copper alloy layer is blanket deposited over a low k dielectric layer and in via openings within the low k dielectric layer. The blanket deposited layer is then anisotropically etch to form horizontal interconnects. The interconnects are annealed to form a metal oxide barrier lining. A second low k dielectric layer is then depositing over the horizontal interconnects. Air gaps can be formed between adjacent interconnects to lower parasitic capacitance therebetween.
摘要翻译： 铜合金层被覆盖在低k电介质层和低k电介质层内的通孔中。 然后将覆盖层沉积层各向异性地蚀刻以形成水平互连。 将互连件退火以形成金属氧化物屏障衬里。 然后第二低k电介质层在水平互连上沉积。 可以在相邻互连之间形成气隙，以降低它们之间的寄生电容。
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