公开(公告)号：US20090216917A1

公开(公告)日：2009-08-27

申请号：US11994270

申请日：2005-06-30

申请人： Uri Shasha ,  Sagi Gurfinkel ,  Gilad Hassid ,  Eran Kahn ,  Yehuda Shvager

发明人： Uri Shasha ,  Sagi Gurfinkel ,  Gilad Hassid ,  Eran Kahn ,  Yehuda Shvager

IPC分类号： G06F13/30 ,  G06F12/00

CPC分类号： G06F13/30

摘要： A method for arbitrating between direct memory access task requests, the method includes receiving multiple DMA task requests; the method is characterized by selecting a DMA task request out of the multiple DMA task requests in response to timing deadlines associated with the DMA tasks. A device that includes an interface, that is adapted to receive DMA task requests; the device is characterized by including an arbiter that is adapted to select a DMA task request out of the multiple DMA task requests in response to timing deadlines associated with the DMA tasks.

摘要翻译： 一种在直接存储器访问任务请求之间进行仲裁的方法，所述方法包括接收多个DMA任务请求; 该方法的特征在于响应于与DMA任务相关联的定时截止时间，从多个DMA任务请求中选择DMA任务请求。 一种包括适于接收DMA任务请求的接口的设备; 该装置的特征在于包括仲裁器，该仲裁器响应于与DMA任务相关联的定时截止时间，适于从多个DMA任务请求中选择DMA任务请求。

公开(公告)号：US20060271061A1

公开(公告)日：2006-11-30

申请号：US10561124

申请日：2004-06-17

申请人： Modechay Beyar ,  Ronen Shavit ,  Oz Vachtenberg ,  Oren Globerman ,  Uri Shasha

发明人： Modechay Beyar ,  Ronen Shavit ,  Oz Vachtenberg ,  Oren Globerman ,  Uri Shasha

IPC分类号： A61B17/68 ,  A61F2/44

CPC分类号： A61B17/8858 ,  A61B1/00071 ,  A61B1/00133 ,  A61B17/7097 ,  A61B17/7098 ,  A61B17/7258 ,  A61B17/7266 ,  A61B17/742 ,  A61B17/8855 ,  A61B2017/00004 ,  A61B2017/00557 ,  A61C8/0033 ,  A61C8/004

摘要： A medical grade deformer, comprising: an axial member; and a pliable tube mounted on said axial member and adapted to be deformed from a first, narrower diameter, configuration to a second, greater diameter, configuration.

摘要翻译： 一种医疗级变形器，包括：轴向构件; 以及安装在所述轴向构件上并适于从第一较窄直径构型变形到第二较大直径构型的柔性管。

公开(公告)号：US08572296B2

公开(公告)日：2013-10-29

申请号：US11994270

申请日：2005-06-30

申请人： Uri Shasha ,  Sagi Gurfinkel ,  Gilad Hassid ,  Eran Kahn ,  Yehuda Shvager

发明人： Uri Shasha ,  Sagi Gurfinkel ,  Gilad Hassid ,  Eran Kahn ,  Yehuda Shvager

IPC分类号： G06F13/28 ,  G06F13/36

CPC分类号： G06F13/30

摘要： A method for arbitrating between direct memory access task requests, the method includes receiving multiple DMA task requests; the method is characterized by selecting a DMA task request out of the multiple DMA task requests in response to timing deadlines associated with the DMA tasks. A device that includes an interface, that is adapted to receive DMA task requests; the device is characterized by including an arbiter that is adapted to select a DMA task request out of the multiple DMA task requests in response to timing deadlines associated with the DMA tasks.

摘要翻译： 一种在直接存储器访问任务请求之间进行仲裁的方法，所述方法包括接收多个DMA任务请求; 该方法的特征在于响应于与DMA任务相关联的定时截止时间，从多个DMA任务请求中选择DMA任务请求。 一种包括适于接收DMA任务请求的接口的设备; 该装置的特征在于包括仲裁器，该仲裁器响应于与DMA任务相关联的定时截止时间，适于从多个DMA任务请求中选择DMA任务请求。

公开(公告)号：US07930444B2

公开(公告)日：2011-04-19

申请号：US11994273

申请日：2005-06-30

申请人： Uri Shasha ,  Sagi Gurfinkel ,  Gilad Hassid ,  Eran Kahn

发明人： Uri Shasha ,  Sagi Gurfinkel ,  Gilad Hassid ,  Eran Kahn

IPC分类号： G06F13/28

CPC分类号： G06F13/28 ,  G06F2213/2802

摘要： A method for controlling multiple DMA tasks, the method includes receiving multiple DMA task requests; the method is characterized by defining multiple buffer descriptors for each of a plurality of DMA channel; wherein at least two buffer descriptors comprise timing information that controls an execution of cyclic time based DMA tasks; selecting a DMA task request out of the multiple DMA task requests; executing a DMA task or a DMA task iteration and updating the buffer descriptor associated with the selected DMA task request to reflect the execution; and jumping to the stage of selecting. A device that includes a memory unit; the device is characterized by including a DMA controller that is adapted to: (i) access at least one buffer descriptor out of multiple buffer descriptors defined for each of a plurality of DMA channel, wherein at least two buffer descriptors comprise timing information that controls an execution of cyclic time based DMA tasks; (ii) receive multiple DMA task requests, (iii) select a DMA task request out of the multiple DMA task requests, and (iv) execute a DMA task or a DMA task iteration and update a buffer descriptor associated with the selected DMA task request to reflect the execution.

摘要翻译： 一种用于控制多个DMA任务的方法，所述方法包括接收多个DMA任务请求; 该方法的特征在于为多个DMA信道中的每一个定义多个缓冲器描述符; 其中至少两个缓冲器描述符包括控制基于循环时间的DMA任务的执行的定时信息; 从多个DMA任务请求中选择DMA任务请求; 执行DMA任务或DMA任务迭代，并更新与所选DMA任务请求相关联的缓冲器描述符以反映执行; 并跳到选择的阶段。 一种包括存储器单元的设备; 该装置的特征在于包括DMA控制器，其适于：（i）从为多个DMA通道中的每一个定义的多个缓冲器描述符中访问至少一个缓冲器描述符，其中至少两个缓冲器描述符包括控制 执行基于循环时间的DMA任务; （ii）接收多个DMA任务请求，（iii）从多个DMA任务请求中选择DMA任务请求，以及（iv）执行DMA任务或DMA任务迭代，并更新与所选择的DMA任务请求相关联的缓冲器描述符 反映执行。

公开(公告)号：US08001430B2

公开(公告)日：2011-08-16

申请号：US11994276

申请日：2005-06-30

申请人： Uri Shasha ,  Sagi Gurfinkel ,  Gilad Hassid ,  Eran Kahn

发明人： Uri Shasha ,  Sagi Gurfinkel ,  Gilad Hassid ,  Eran Kahn

IPC分类号： G06F11/00

CPC分类号： G06F13/28

摘要： A method for controlling an execution of a first DMA task, the method includes comprises monitoring an execution of the first DMA task, the method characterized by including defining a first DMA task execution interval and a first DMA task execution sub-interval; and performing a first possible timing violation responsive operation if the first DMA task was not completed during the first DMA task execution sub-interval. A device having a first DMA task controlling capabilities, the device includes a memory unit; characterized by including a DMA controller that is adapted to monitor an execution of the first DMA task that involves an access to the memory unit, and to perform a first possible timing violation responsive operation if the first DMA task was not completed during a first DMA task execution sub-interval.

摘要翻译： 一种用于控制第一DMA任务的执行的方法，所述方法包括监视所述第一DMA任务的执行，所述方法的特征在于包括定义第一DMA任务执行间隔和第一DMA任务执行子间隔; 以及如果在所述第一DMA任务执行子间隔期间所述第一DMA任务未完成，则执行第一可能的定时违反响应操作。 一种具有第一DMA任务控制能力的设备，所述设备包括存储器单元; 其特征在于包括DMA控制器，其适于监视涉及对所述存储器单元的访问的所述第一DMA任务的执行，以及如果在所述第一DMA任务期间未完成所述第一DMA任务，则执行第一可能的定时违反响应操作 执行子间隔。

公开(公告)号：US20100064069A1

公开(公告)日：2010-03-11

申请号：US11994273

申请日：2005-06-30

申请人： Uri Shasha

发明人： Uri Shasha

IPC分类号： G06F13/28

CPC分类号： G06F13/28 ,  G06F2213/2802

摘要： A method for controlling multiple DMA tasks, the method includes receiving multiple DMA task requests; the method is characterized by defining multiple buffer descriptors for each of a plurality of DMA channel; wherein at least two buffer descriptors comprise timing information that controls an execution of cyclic time based DMA tasks; selecting a DMA task request out of the multiple DMA task requests; executing a DMA task or a DMA task iteration and updating the buffer descriptor associated with the selected DMA task request to reflect the execution; and jumping to the stage of selecting. A device that includes a memory unit; the device is characterized by including a DMA controller that is adapted to: (i) access at least one buffer descriptor out of multiple buffer descriptors defined for each of a plurality of DMA channel, wherein at least two buffer descriptors comprise timing information that controls an execution of cyclic time based DMA tasks; (ii) receive multiple DMA task requests, (iii) select a DMA task request out of the multiple DMA task requests, and (iv) execute a DMA task or a DMA task iteration and update a buffer descriptor associated with the selected DMA task request to reflect the execution.

摘要翻译： 一种用于控制多个DMA任务的方法，所述方法包括接收多个DMA任务请求; 该方法的特征在于为多个DMA信道中的每一个定义多个缓冲器描述符; 其中至少两个缓冲器描述符包括控制基于循环时间的DMA任务的执行的定时信息; 从多个DMA任务请求中选择DMA任务请求; 执行DMA任务或DMA任务迭代，并更新与所选DMA任务请求相关联的缓冲器描述符以反映执行; 并跳到选择的阶段。 一种包括存储器单元的设备; 该装置的特征在于包括DMA控制器，其适于：（i）从为多个DMA通道中的每一个定义的多个缓冲器描述符中访问至少一个缓冲器描述符，其中至少两个缓冲器描述符包括控制 执行基于循环时间的DMA任务; （ii）接收多个DMA任务请求，（iii）从多个DMA任务请求中选择DMA任务请求，以及（iv）执行DMA任务或DMA任务迭代，并更新与所选择的DMA任务请求相关联的缓冲器描述符 反映执行。

公开(公告)号：US20090125647A1

公开(公告)日：2009-05-14

申请号：US11994278

申请日：2005-06-30

申请人： Uri Shasha ,  Sagi Gurfinkel ,  Gilad Hassid ,  Eran Kahn

发明人： Uri Shasha ,  Sagi Gurfinkel ,  Gilad Hassid ,  Eran Kahn

IPC分类号： G06F3/00

CPC分类号： G06F13/28

摘要： A method for executing a DMA task, the method includes receiving a request to execute a DMA task; the method characterized by including: defining inter-buffer jumping points at substantially an end of one or more dimensions of each multidimensional buffer out of a plurality of multidimensional buffers; and executing multiple DMA sub-tasks, wherein the executing includes jumping between buffers at the inter-buffer jumping points. A device hat includes at least one memory unit and a DMA controller adapted to access the memory unit; the device is characterized by being adapted to implement multidimensional buffers within the at least one memory unit; wherein the DMA controller is adapted to execute multiple DMA sub-tasks, wherein the execution comprises jumping between buffers at inter-buffer jumping points; and wherein the inter-buffer jumping points are defined at substantially an end of one or more dimensions of each multidimensional buffer out of a plurality of multidimensional buffers.

摘要翻译： 一种用于执行DMA任务的方法，所述方法包括接收执行DMA任务的请求; 该方法的特征在于包括：在多个多维缓冲器中的每个多维缓冲器的一个或多个维度的基本上结束处定义缓冲器间跳跃点; 以及执行多个DMA子任务，其中所述执行包括在所述缓冲间间跳跃点处的缓冲器之间跳转。 装置帽包括至少一个存储器单元和适于访问存储器单元的DMA控制器; 该装置的特征在于适于在至少一个存储器单元内实现多维缓冲器; 其中所述DMA控制器适于执行多个DMA子任务，其中所述执行包括在缓冲器间跳跃点处的缓冲器之间跳转; 并且其中所述缓冲间间跳跃点被限定在多个多维缓冲器中的每个多维缓冲器的一个或多个维度的基本上的一端。

公开(公告)号：US20090144589A1

公开(公告)日：2009-06-04

申请号：US11994276

申请日：2005-06-30

申请人： Uri Shasha ,  Sagi Gurfinkel ,  Gilad Hassid ,  Eran Kahn

发明人： Uri Shasha ,  Sagi Gurfinkel ,  Gilad Hassid ,  Eran Kahn

IPC分类号： G06F11/07 ,  G06F13/24 ,  G06F13/28

CPC分类号： G06F13/28

摘要： A method for controlling an execution of a first DMA task, the method includes comprises monitoring an execution of the first DMA task, the method characterized by including defining a first DMA task execution interval and a first DMA task execution sub-interval; and performing a first possible timing violation responsive operation if the first DMA task was not completed during the first DMA task execution sub-interval. A device having a first DMA task controlling capabilities, the device includes a memory unit; characterized by including a DMA controller that is adapted to monitor an execution of the first DMA task that involves an access to the memory unit, and to perform a first possible timing violation responsive operation if the first DMA task was not completed during a first DMA task execution sub-interval.

摘要翻译： 一种用于控制第一DMA任务的执行的方法，所述方法包括监视所述第一DMA任务的执行，所述方法的特征在于包括定义第一DMA任务执行间隔和第一DMA任务执行子间隔; 以及如果在所述第一DMA任务执行子间隔期间所述第一DMA任务未完成，则执行第一可能的定时违反响应操作。 一种具有第一DMA任务控制能力的设备，所述设备包括存储器单元; 其特征在于包括DMA控制器，其适于监视涉及对所述存储器单元的访问的所述第一DMA任务的执行，以及如果在所述第一DMA任务期间未完成所述第一DMA任务，则执行第一可能的定时违反响应操作 执行子间隔。