Abstract:
The claimed invention discloses system comprising a plurality of logical nodes comprised in a single or plurality of stages, with defined properties and resources associated with each node, for reducing compute resources, said system further comprising: at least a recirculating ring buffer holding only any one of a control information, input, and, or out data necessary to stream a temporary data between node and, or nodes in an execution graph, thereby reducing size of said recirculating ring buffer; said recirculating ring buffer being sufficiently reduced in size to reside in an on-chip cache, such that any one of the control information, input, and, or out data between node and, or nodes need not be stored in memory; wherein the control information further comprises a command related to invalidating any one of the input and, or out data held in a recirculating ring data buffer, clearing the buffer of tasked data; and wherein a producer is stalled from writing any more control information into a recirculating ring command buffer upon the buffer being full, preventing command buffer over-writing, and thereby reducing compute resources associated with a DRAM memory transaction.
Abstract:
In one embodiment, a method of performing video image decoding includes the following. A compressed video image is downsampled in the frequency domain. The downsampled video image is inverse transformed. Motion compensation for the downsampled image is performed in the spatial domain.
Abstract:
A texture data reading apparatus includes a cache memory including a plurality of read ports and a plurality of regions to store pixel texture data. An address comparator includes a plurality of input ports to receive incoming pixels, wherein the address comparator compares the memory addresses associated with the incoming pixels to determine which regions of cache memory are accessed. A cache lookup device accesses new texture data from the cache memory for the incoming pixels in the same clock cycle in response to the number of memory regions accessed being less than or equal to the number of cache memory read ports.
Abstract:
A machine readable storage media containing executable program instructions which when executed cause a digital processing system to seta plurality of operands and operators. A plurality of texture maps are sent to a processor for texture compositing. Operands are selected for a texture operation. A first logic is used wherein if the circulation of blend stages is equal to a number of blend stages, then a color saturation is performed, and a second logic that if the circulation number of blend stages does not equal the number of blend stages then at least one operand is selected for another texture compositing operation.
Abstract:
A method and apparatus for improved processing of digitized moving pictures. A motion vector for field frame processing is produced using fewer pixels from the source image and fewer coefficients than are required by the prior art. This allows field frame motion to be processed using no more pixels than are required for other forms of motion processing, which in turn reduces the circuitry and processing time required. A reduction in the pixel processing requirement allows less circuitry to be used for this processing with equivalent throughput. Alternatively, it allows for improved throughput with an approximately equivalent amount of circuitry.
Abstract:
The claimed invention discloses system comprising a plurality of logical nodes comprised in a single or plurality of stages, with defined properties and resources associated with each node, for reducing compute resources, said system further comprising: at least a recirculating ring buffer holding only any one of a control information, input, and, or out data necessary to stream a temporary data between node and, or nodes in an execution graph, thereby reducing size of said recirculating ring buffer; said recirculating ring buffer being sufficiently reduced in size to reside in an on-chip cache, such that any one of the control information, input, and, or out data between node and, or nodes need not be stored in memory; wherein the control information further comprises a command related to invalidating any one of the input and, or out data held in a recirculating ring data buffer, clearing the buffer of tasked data; and wherein a producer is stalled from writing any more control information into a recirculating ring command buffer upon the buffer being full, preventing command buffer over-writing, and thereby reducing compute resources associated with a DRAM memory transaction.
Abstract:
A machine readable storage media containing executable program instructions which when executed cause a digital processing system to seta plurality of operands and operators. A plurality of texture maps are sent to a processor for texture compositing. Operands are selected for a texture operation. A first logic is used wherein if the circulation of blend stages is equal to a number of blend stages, then a color saturation is performed, and a second logic that if the circulation number of blend stages does not equal the number of blend stages then at least one operand is selected for another texture compositing operation.
Abstract:
According to one embodiment, a circuit for generating motion compensated video includes a means for translating a macroblock into one or more motion compensation commands having associated correction data related to the macroblock. The motion compensation command is an autonomous command that supports a plurality of motion compensation modes. Also, the circuit includes a means for receiving the motion compensation command, a means for storing the correction data in a memory according to a first order corresponding to the motion compensation command and a means for performing frame prediction operations in response to the motion compensation command. Moreover, the circuit includes a means for reading the correction data from the memory according to a second order and a means for combining the correction data with results from the frame prediction operations to generate an output video frame.
Abstract:
A method and apparatus for image scaling is provided. A 3D pipeline comprises a command stream controller to enable a rectangle mode. The 3D pipeline including a windower to produce addresses for the rectangle defined by the vertices. A filter interpolates between neighboring points, based on relative location, to generate attributes for each pixel. A color calculator aligns output data and writes the output data to a destination surface.
Abstract:
A circuit for blending video signals and subpicture signals is provided. The circuit includes a palette to output at least one subpicture value based on a palette index. The circuit also includes an alpha-blend unit coupled to the subpicture palette to blend a set of luminance values of a video signal with a set of luminance values of a subpicture signal in one pass and to blend a set of chrominance values of a video signal with a set of chrominance values of the subpicture signal in a separate pass, the luminance and chrominance values are provided to the alpha-blend unit in a planar format. The video signals may be provided and blended in a YUV 4:2:0 format. In addition, a single dual-purpose palette can be used for both texturing and alpha-blending.