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    Method and apparatus for performing post-placement functional decomposition for field programmable gate arrays
    9.
    发明授权
    Method and apparatus for performing post-placement functional decomposition for field programmable gate arrays 有权
    用于对现场可编程门阵列执行放置后功能分解的方法和装置

    公开(公告)号：US07290239B1

    公开(公告)日：2007-10-30

    申请号：US10858300

    申请日：2004-06-01

    申请人： Deshanand Singh ,  Valavan Manohararajah ,  Karl Schabas

    发明人： Deshanand Singh ,  Valavan Manohararajah ,  Karl Schabas

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5054

    摘要： A method for designing a system on a target device utilizing field programmable gate arrays (FPGAs) includes synthesizing a design for the system. Components in the design are mapped onto resources on the target device. Placement locations are determined for the components on the target device. The design for the system is restructured after placement locations for the components are determined to improve timing for the system.

    摘要翻译： 利用现场可编程门阵列（FPGA）在目标设备上设计系统的方法包括合成系统的设计。 设计中的组件映射到目标设备上的资源。 确定目标设备上的组件的位置位置。 系统的设计在重新组建了组件的放置位置后才能改进系统的时序。

    Systems and methods for mapping arbitrary logic functions into synchronous embedded memories
    10.
    发明授权
    Systems and methods for mapping arbitrary logic functions into synchronous embedded memories 有权
    将任意逻辑功能映射到同步嵌入式存储器中的系统和方法

    公开(公告)号：US07797666B1

    公开(公告)日：2010-09-14

    申请号：US12244635

    申请日：2008-10-02

    申请人： Gordon Chiu ,  Deshanand Singh ,  Valavan Manohararajah ,  Stephen Brown

    发明人： Gordon Chiu ,  Deshanand Singh ,  Valavan Manohararajah ,  Stephen Brown

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5054

    摘要： Systems and methods are provided for mapping logic functions from logic elements (“LEs”) into synchronous embedded memory blocks (“EMBs”) of programmable logic devices (“PLDs”). This technique increases the amount of logic that can fit into the PLD. Where area savings are significant, smaller PLDs may be selected to implement a particular circuit. One aspect of the invention relates to methods for identifying sequential cones of logic that may be mapped into synchronous EMBs. After the sequential logic cones are identified for mapping into a synchronous EMB, the logic cone may be selected, expanded, restructured, and retimed, as necessary, to implement the mapping. Another aspect of the invention relates to techniques for handling architectural restrictions of synchronous EMBs, such as the inability to implement the asynchronous behavior of synchronous logic.

    摘要翻译： 提供了将逻辑元件（“LE”）的逻辑功能映射到可编程逻辑器件（“PLD”）的同步嵌入式存储器块（“EMB”）的系统和方法。 这种技术增加了可以适应PLD的逻辑量。 如果区域节省很大，则可以选择较小的PLD来实现特定的电路。 本发明的一个方面涉及用于识别可以映射到同步EMB中的逻辑顺序锥的方法。 在确定用于映射到同步EMB中的顺序逻辑锥之后，可以根据需要选择，扩展，重构和重新定时，以实现映射。 本发明的另一方面涉及用于处理同步EMB的架构限制的技术，诸如不能实现同步逻辑的异步行为。