公开(公告)号：US06326266B1

公开(公告)日：2001-12-04

申请号：US09141849

申请日：1998-08-27

Applicant: Claudio Brambilla ,  Valerio Cassio ,  Paolo Caprara ,  Manlio Sergio Creda

Inventor： Claudio Brambilla ,  Valerio Cassio ,  Paolo Caprara ,  Manlio Sergio Creda

IPC: H01L21336

CPC classification number: H01L27/11526 ,  H01L27/105 ,  H01L27/11546

Abstract: A method of manufacturing a semiconductor virtual ground memory device having a matrix of floating gate memory cells formed on a semiconductor substrate with a plurality of continuous bit lines extending across the substrate as discrete parallel stripes. The device also includes a circuit portion for selection transistors and decode and address circuit portions having P-channel and N-channel MOS transistors. According to the method, N-wells are formed in at least one substrate portion to accommodate the P-channel transistors, active areas of all transistors are defined using a screening mask, and then an isolation layer is grown through the apertures of the screening mask. The screening mask is not open over the matrix region of the memory cells.

Abstract translation: 一种半导体虚拟接地存储器件的制造方法，该半导体虚拟接地存储器件具有形成在半导体衬底上的浮置栅极存储器单元的矩阵，该多个连续位线跨越衬底延伸为离散的平行条纹。 该器件还包括用于选择晶体管的电路部分，以及具有P沟道和N沟道MOS晶体管的解码和寻址电路部分。 根据该方法，在至少一个衬底部分中形成N阱以容纳P沟道晶体管，使用屏蔽掩模限定所有晶体管的有源区，然后通过掩模掩模的孔生长隔离层 。 筛选掩模在存储单元的矩阵区域上不开放。

公开(公告)号：US6063663A

公开(公告)日：2000-05-16

申请号：US139909

申请日：1998-08-26

Applicant: Paolo Caprara ,  Claudio Brambilla ,  Manlio Sergio Cereda ,  Valerio Cassio

Inventor： Paolo Caprara ,  Claudio Brambilla ,  Manlio Sergio Cereda ,  Valerio Cassio

IPC: H01L21/8247 ,  H01L27/105 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792 ,  H01L21/336

CPC classification number: H01L27/11526 ,  H01L27/105 ,  H01L27/11541 ,  H01L27/11543

Abstract: A method is provided of manufacturing a P-channel native MOS transistor in a circuit integrated on a semiconductor which also includes a matrix of non-volatile memory cells of the floating gate type with two polysilicon levels having an interpoly dielectric layer sandwiched between the two polysilicon levels. The method has the following steps: (1) masking and defining active areas of the discrete integrated devices; (2) masking and defining the first polysilicon level using a Poly1 mask; and (3) masking and defining an intermediate dielectric layer using a matrix mask. The length of the native threshold channel of the native transistor is defined by means of the matrix mask and by etching away the interpoly dielectric layer. A subsequent step of masking and defining the second polysilicon level provides for the use of a Poly2 mask which extends the active area of the transistor with a greater width than the previous mask in order to enable, by subsequent etching, the two polysilicon levels to overlap in self-alignment over the channel region.

Abstract translation: 提供了一种在集成在半导体上的电路中制造P沟道天然MOS晶体管的方法，该半导体还包括浮置型非易失性存储单元的矩阵，其中两个多晶硅层具有夹在两个多晶硅之间的多晶硅间介电层 水平。 该方法具有以下步骤：（1）屏蔽和定义离散集成器件的有源区; （2）使用Poly1掩模掩蔽和限定第一多晶硅层; 和（3）使用矩阵掩模掩蔽和限定中间介电层。 天生晶体管的天生阈值通道的长度通过矩阵掩模定义，并通过蚀刻掉多余介电层。 掩蔽和限定第二多晶硅级别的后续步骤提供了使用Poly2掩模，该Poly2掩模以比先前掩模更大的宽度延伸晶体管的有源区，以便通过随后的蚀刻使两个多晶硅层重叠 在通道区域上自对准。