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1.发明授权Method for manufacturing a native MOS P-channel transistor with a process for manufacturing non-volatile memories 有权用于制造非易失性存储器的工艺的原生MOS P沟道晶体管的制造方法
公开(公告)号：US6063663A
公开(公告)日：2000-05-16
申请号：US139909
申请日：1998-08-26
IPC分类号： H01L21/8247 , H01L27/105 , H01L27/115 , H01L29/788 , H01L29/792 , H01L21/336
CPC分类号： H01L27/11526 , H01L27/105 , H01L27/11541 , H01L27/11543
摘要： A method is provided of manufacturing a P-channel native MOS transistor in a circuit integrated on a semiconductor which also includes a matrix of non-volatile memory cells of the floating gate type with two polysilicon levels having an interpoly dielectric layer sandwiched between the two polysilicon levels. The method has the following steps: (1) masking and defining active areas of the discrete integrated devices; (2) masking and defining the first polysilicon level using a Poly1 mask; and (3) masking and defining an intermediate dielectric layer using a matrix mask. The length of the native threshold channel of the native transistor is defined by means of the matrix mask and by etching away the interpoly dielectric layer. A subsequent step of masking and defining the second polysilicon level provides for the use of a Poly2 mask which extends the active area of the transistor with a greater width than the previous mask in order to enable, by subsequent etching, the two polysilicon levels to overlap in self-alignment over the channel region.
摘要翻译： 提供了一种在集成在半导体上的电路中制造P沟道天然MOS晶体管的方法，该半导体还包括浮置型非易失性存储单元的矩阵，其中两个多晶硅层具有夹在两个多晶硅之间的多晶硅间介电层 水平。 该方法具有以下步骤：（1）屏蔽和定义离散集成器件的有源区; （2）使用Poly1掩模掩蔽和限定第一多晶硅层; 和（3）使用矩阵掩模掩蔽和限定中间介电层。 天生晶体管的天生阈值通道的长度通过矩阵掩模定义，并通过蚀刻掉多余介电层。 掩蔽和限定第二多晶硅级别的后续步骤提供了使用Poly2掩模，该Poly2掩模以比先前掩模更大的宽度延伸晶体管的有源区，以便通过随后的蚀刻使两个多晶硅层重叠 在通道区域上自对准。
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2.发明授权Method for autoaligning overlapped lines of a conductive material in integrated electronic circuits 失效在集成电子电路中自动对准导电材料的重叠线的方法公开(公告)号：US06350671B1
公开(公告)日：2002-02-26
申请号：US09579778
申请日：2000-05-26
IPC分类号： H01L214263
CPC分类号： H01L21/76897 , H01L21/76816 , H01L21/76831 , H01L21/76877 , H01L21/76885 , H01L2924/3011
摘要： A method for autoaligning lines of a conductive material in circuits integrated on a semiconductor substrate is presented. The method includes forming several regions projecting from the substrate surface and aligned to one another, and forming a fill layer in the gaps between the projecting regions. The fill layer is planarized to expose the regions, and a portion of the regions is removed to form holes at the locations of the regions. Next an insulating layer is formed in the holes. The insulating layer is selectively removed to form spacers along the edges of said holes and at least one conductive layer is deposited over the exposed surface. Later, a step of photolithograpy with a mask is performed and the conductive layer is etched to define lines and collimate them to the underlying regions.
摘要翻译： 提出了一种在集成在半导体衬底上的电路中自动对准导电材料线的方法。 该方法包括形成从基板表面突出并且彼此对准的若干区域，并且在突出区域之间的间隙中形成填充层。 将填充层平坦化以暴露区域，并且去除部分区域以在区域的位置处形成孔。 接下来，在孔中形成绝缘层。 选择性地去除绝缘层以沿着所述孔的边缘形成间隔物，并且至少一个导电层沉积在暴露的表面上。 之后，进行用掩模进行光刻的步骤，蚀刻导电层以限定线并将它们准直到下面的区域。
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公开(公告)号：US07115472B2
公开(公告)日：2006-10-03
申请号：US10964049
申请日：2004-10-12
IPC分类号： H01L21/8242
CPC分类号： H01L27/11568 , H01L27/115 , H01L29/792 , H01L29/7923
摘要： A process for manufacturing a dual charge storage location electrically programmable memory cell that includes the steps of forming a central insulated gate over a semiconductor substrate; forming physically separated charge-confining layers stack portions of a dielectric-charge trapping material-dielectric layers stack at the sides of the central gate, the charge trapping material layer in each charge-confining layers stack portion forming a charge storage element; forming side control gates over each of the charge-confining layers stack portions; forming memory cell source/drain regions laterally to the side control gates; and electrically connecting the side control gates to the central gate. Each of the charge-confining layers stack portions at the sides of the central gate is formed with an “L” shape, with a base charge-confining layers stack portion lying on the substrate surface and an upright charge-confining layers stack portion lying against a respective side of the insulated gate.
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公开(公告)号：US06825523B2
公开(公告)日：2004-11-30
申请号：US10267033
申请日：2002-10-07
IPC分类号： H01L2976
CPC分类号： H01L27/11568 , H01L27/115 , H01L29/792 , H01L29/7923
摘要： A process for manufacturing a dual charge storage location electrically programmable memory cell that includes the steps of forming a central insulated gate over a semiconductor substrate; forming physically separated charge-confining layers stack portions of a dielectric-charge trapping material-dielectric layers stack at the sides of the central gate, the charge trapping material layer in each charge-confining layers stack portion forming a charge storage element; forming side control gates over each of the charge-confining layers stack portions; forming memory cell source/drain regions laterally to the side control gates; and electrically connecting the side control gates to the central gate. Each of the charge-confining layers stack portions at the sides of the central gate is formed with an “L” shape, with a base charge-confining layers stack portion lying on the substrate surface and an upright charge-confining layers stack portion lying against a respective side of the insulated gate.
摘要翻译： 一种用于制造双电荷存储位置电可编程存储单元的方法，包括在半导体衬底上形成中心绝缘栅极的步骤; 形成物理上分离的电荷限制层，堆叠在中心栅极侧的介质电荷捕获材料 - 电介质层堆叠部分，每个电荷限制层堆叠部分中的电荷捕获材料层形成电荷存储元件; 在每个电荷限制层堆叠部分上形成侧面控制栅极; 在侧控制门侧面形成存储单元源极/漏极区; 并将侧面控制门电连接到中央门。 在中心栅极侧面的电荷限制层堆叠部分中的每一个形成为“L”形，基底电荷限制层堆叠部分位于衬底表面上，并且垂直电荷限制层堆叠部分抵靠 绝缘门的相应侧。
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5.发明授权Process for manufacturing semiconductor integrated memory devices with cells matrix having virtual ground 有权具有具有虚拟接地的单元矩阵的半导体集成存储器件的制造工艺公开(公告)号：US06365456B1
公开(公告)日：2002-04-02
申请号：US09507777
申请日：2000-02-18
IPC分类号： H01L21336
CPC分类号： H01L27/11521 , H01L21/0337 , H01L29/66825
摘要： A process for manufacturing electronic semiconductor integrated memory devices having a virtual ground and comprising at least a matrix of floating gate memory cells is presented. In the memory device, the matrix is formed on a semiconductor substrate with a number of continuous bit lines extending across the substrate as discrete parallel strips. The process begins by growing an oxide layer over the matrix region and depositing over the semiconductor throughout a stack structure which comprises a first conductor layer, a first dielectric layer, and a second conductor layer. Then a second dielectric layer is deposited over the stack structure, and floating gate regions are defined by photolithography using a mask of “POLY1 along a first direction”, to thereby define in the dielectric layer, a plurality of parallel strips which delimit a first dimension of floating gate regions. Next the dielectric layer is etched away to define a plurality of parallel dielectric strips and a number of dielectric islands are defined by photolithography using a mask of “POLY1 along a second direction” in the plurality of parallel strips. The dielectric layer is etched to define the plurality of islands. Finally, the stack structure and the thin gate oxide layer are etched to define gate regions of the matrix cells using said oxide island.
摘要翻译： 本发明提供一种制造具有虚拟接地并且至少包括浮动栅极存储单元矩阵的电子半导体集成存储器件的工艺。 在存储器件中，矩阵形成在半导体衬底上，多个连续的位线作为离散的平行条延伸穿过衬底。 该过程开始于在矩阵区域上生长氧化物层并且在包括第一导体层，第一介电层和第二导体层的整个堆叠结构中沉积在半导体上。 然后在堆叠结构上沉积第二介电层，并且通过使用“POLY1沿着第一方向”的掩模的光刻法定义浮动栅极区域，从而在电介质层中限定多个平行的条，其限定第一维度 的浮动门区域。 接下来，蚀刻掉电介质层以限定多个平行的介质条，并且通过使用在多个平行条带中的沿着第二方向的“POLY1”的掩模的光刻来限定多个介电岛。 蚀刻介电层以限定多个岛。 最后，使用所述氧化物岛蚀刻所述堆叠结构和所述薄栅极氧化物层以限定所述矩阵单元的栅极区域。
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6.发明授权Method of manufacturing an EPROM memory device having memory cells organized in a tablecloth matrix 失效具有组织在台布矩阵中的存储单元的EPROM存储器件的制造方法公开(公告)号：US06326266B1
公开(公告)日：2001-12-04
申请号：US09141849
申请日：1998-08-27
IPC分类号： H01L21336
CPC分类号： H01L27/11526 , H01L27/105 , H01L27/11546
摘要： A method of manufacturing a semiconductor virtual ground memory device having a matrix of floating gate memory cells formed on a semiconductor substrate with a plurality of continuous bit lines extending across the substrate as discrete parallel stripes. The device also includes a circuit portion for selection transistors and decode and address circuit portions having P-channel and N-channel MOS transistors. According to the method, N-wells are formed in at least one substrate portion to accommodate the P-channel transistors, active areas of all transistors are defined using a screening mask, and then an isolation layer is grown through the apertures of the screening mask. The screening mask is not open over the matrix region of the memory cells.
摘要翻译： 一种半导体虚拟接地存储器件的制造方法，该半导体虚拟接地存储器件具有形成在半导体衬底上的浮置栅极存储器单元的矩阵，该多个连续位线跨越衬底延伸为离散的平行条纹。 该器件还包括用于选择晶体管的电路部分，以及具有P沟道和N沟道MOS晶体管的解码和寻址电路部分。 根据该方法，在至少一个衬底部分中形成N阱以容纳P沟道晶体管，使用屏蔽掩模限定所有晶体管的有源区，然后通过掩模掩模的孔生长隔离层 。 筛选掩模在存储单元的矩阵区域上不开放。
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公开(公告)号：US20050064654A1
公开(公告)日：2005-03-24
申请号：US10964049
申请日：2004-10-12
申请人： Paolo Caprara , Claudio Brambilla , Manlio Cereda
发明人： Paolo Caprara , Claudio Brambilla , Manlio Cereda
IPC分类号： H01L21/8247 , H01L21/8246 , H01L27/115 , H01L29/788 , H01L29/792 , H01L21/20
CPC分类号： H01L27/11568 , H01L27/115 , H01L29/792 , H01L29/7923
摘要： A process for manufacturing a dual charge storage location electrically programmable memory cell that includes the steps of forming a central insulated gate over a semiconductor substrate; forming physically separated charge-confining layers stack portions of a dielectric-charge trapping material-dielectric layers stack at the sides of the central gate, the charge trapping material layer in each charge-confining layers stack portion forming a charge storage element; forming side control gates over each of the charge-confining layers stack portions; forming memory cell source/drain regions laterally to the side control gates; and electrically connecting the side control gates to the central gate. Each of the charge-confining layers stack portions at the sides of the central gate is formed with an “L” shape, with a base charge-confining layers stack portion lying on the substrate surface and an upright charge-confining layers stack portion lying against a respective side of the insulated gate.
摘要翻译： 一种用于制造双电荷存储位置电可编程存储单元的方法，包括在半导体衬底上形成中心绝缘栅极的步骤; 形成物理上分离的电荷限制层，堆叠在中心栅极侧的介电电荷俘获材料 - 电介质层堆叠部分，每个电荷限制层堆叠部分中的电荷捕获材料层形成电荷存储元件; 在每个电荷限制层堆叠部分上形成侧面控制栅极; 在侧控制门侧面形成存储单元源极/漏极区; 并将侧面控制门电连接到中央门。 在中心栅极侧面的电荷限制层堆叠部分中的每一个形成为“L”形，基底电荷限制层堆叠部分位于衬底表面上，并且垂直电荷限制层堆叠部分抵靠 绝缘门的相应侧。
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8.发明授权Process for manufacturing semiconductor integrated memory devices with cells matrix having virtual ground 有权具有具有虚拟接地的单元矩阵的半导体集成存储器件的制造工艺公开(公告)号：US06300195B1
公开(公告)日：2001-10-09
申请号：US09512900
申请日：2000-02-25
IPC分类号： H01L21336
CPC分类号： H01L27/11521
摘要： A process for manufacturing electronic semiconductor integrated electronic memory devices having virtual ground and including at least a matrix of floating gate memory cells formed on a semiconductor substrate with a plurality of continuous bit lines extending across the substrate as discrete parallel strips begins with forming an oxide layer over the matrix region. Then, the semiconductor throughout is deposited with a stack structure which includes a first conductor layer, a first dielectric layer, and second conductor layer. Next, a second dielectric layer is formed. Floating gate regions are defined by photolithography using a mask of “POLY1 along a first predetermined direction”, and associated etching, to define, in the stack structure, a plurality of parallel openings. These openings are implanted to confer a predetermined conductivity on the bit line regions. Next, the parallel openings are filled with a photo-sensitive material to protect the matrix bit lines.
摘要翻译： 一种用于制造具有虚拟接地并且至少包括形成在半导体衬底上的浮动栅极存储器单元的矩阵的电子半导体集成电子存储器件的工艺，其具有跨越衬底延伸的多个连续位线作为离散的平行条带，开始形成氧化物层 超过矩阵区域。 然后，整个半导体层叠有包括第一导体层，第一介电层和第二导体层的堆叠结构。 接下来，形成第二电介质层。 通过使用“沿着第一预定方向的”POLY1“掩模的光刻法和相关联的蚀刻来限定浮动栅极区域，以在堆叠结构中限定多个平行的开口。 植入这些开口以赋予位线区域上预定的导电性。 接下来，平行的开口填充有光敏材料以保护矩阵位线。
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9.发明授权Method for forming contactless MOS transistors and resulting devices, especially for use in non-volatile memory arrays 有权用于形成非接触MOS晶体管和所得器件的方法，特别是用于非易失性存储器阵列公开(公告)号：US06251736B1
公开(公告)日：2001-06-26
申请号：US09473368
申请日：1999-12-28
IPC分类号： H01L21336
CPC分类号： H01L27/11521 , Y10S438/976
摘要： A process for manufacturing a MOS transistor and especially a MOS transistor used for non-volatile memory cells is presented. At the start of the manufacturing, a semiconductor substrate having a first type of conductivity is covered by a gate oxide layer. A gate electrode is formed over the gate oxide layer, which is a stacked gate when the MOS transistor is used in a non-volatile memory. Covering the gate electrode is a covering oxide that is formed over the gate oxide layer, the gate electrode, and around the gate electrode. Next, a dopant of a second type of conductivity is implanted to provide implant regions adjacent to the gate electrode. Subjecting the semiconductor to thermal treatments allows the implanted regions to diffuse into the semiconductor substrate under the gate electrode and form a gradual junction drain and source region of the MOS transistor.
摘要翻译： 本发明提供一种制造用于非易失性存储单元的MOS晶体管，特别是MOS晶体管的工艺。 在制造开始时，具有第一类导电性的半导体衬底被栅极氧化物层覆盖。 在MOS晶体管用于非易失性存储器中的栅极氧化物层上形成栅电极，栅极氧化层是层叠栅极。 覆盖栅电极是在栅极氧化物层，栅电极和栅电极周围形成的覆盖氧化物。 接下来，注入第二类导电性的掺杂剂以提供邻近栅电极的注入区。 使半导体进行热处理允许注入区域扩散到栅电极下方的半导体衬底中，并形成MOS晶体管的逐渐连接漏极和源极区域。
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10.发明授权MOS device and process for manufacturing MOS devices using dual-polysilicon layer technology 有权MOS器件和使用双重多晶硅层技术制造MOS器件的工艺公开(公告)号：US07023047B2
公开(公告)日：2006-04-04
申请号：US10745295
申请日：2003-12-23
IPC分类号： H01L29/72
CPC分类号： H01L27/11526 , H01L21/28273 , H01L27/105 , H01L27/11524 , H01L27/11534
摘要： An MOS device has a stack and a passivation layer covering the stack. The stack is formed by a first polysilicon region and by a second polysilicon region arranged on top of one another and separated by an intermediate dielectric region. An electrical connection region, formed by a column structure substantially free of steps, extends through the passivation layer, the second polysilicon region and the intermediate dielectric region, and terminates in contact with the first polysilicon region so as to electrically contacting the first polysilicon region and the second polysilicon region. Fabrication of the electrical connection region requires just one mask.
摘要翻译： MOS器件具有覆盖堆叠的堆叠层和钝化层。 堆叠由第一多晶硅区域和由彼此顶部布置并由中间介电区域隔开的第二多晶硅区域形成。 由基本上没有台阶的柱结构形成的电连接区域延伸穿过钝化层，第二多晶硅区域和中间介质区域，并且终止于与第一多晶硅区域接触，从而使第一多晶硅区域和 第二多晶硅区域。 电连接区域的制造仅需要一个掩模。
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