公开(公告)号：US08072974B1

公开(公告)日：2011-12-06

申请号：US12175702

申请日：2008-07-18

Applicant: Naveen K. Jain ,  Venkata Rangavajjhala

Inventor： Naveen K. Jain ,  Venkata Rangavajjhala

IPC: H04L12/56

CPC classification number: H04L49/3036 ,  H04L49/103 ,  H04L49/3063

Abstract: A network processing device having multiple processing engines capable of providing multi-context parallel processing is disclosed. The device includes a receiver and a packet processor, wherein the receiver is capable of receiving packets at a predefined packet flow rate. The packet processor, in one embodiment, includes multiple processing engines, wherein each processing engine is further configured to include multiple context processing components. The context processing components are used to provide multi-context parallel processing to increase throughput.

Abstract translation: 公开了具有能够提供多上下文并行处理的多个处理引擎的网络处理装置。 该设备包括接收机和分组处理器，其中接收机能够以预定的分组流速接收分组。 在一个实施例中，分组处理器包括多个处理引擎，其中每个处理引擎还被配置为包括多个上下文处理组件。 上下文处理组件用于提供多上下文并行处理以增加吞吐量。

公开(公告)号：US07353288B1

公开(公告)日：2008-04-01

申请号：US09978927

申请日：2001-10-17

Applicant: Venkata Rangavajjhala ,  Venkata Kalapatapu

Inventor： Venkata Rangavajjhala ,  Venkata Kalapatapu

IPC: G06F15/16

CPC classification number: H04J3/0623 ,  H04J3/1611 ,  H04J2203/0012 ,  H04J2203/0026 ,  H04J2203/006 ,  H04J2203/0073

Abstract: Multiple frames of SDH framed data are received. Each frame has an overhead portion and a payload portion. The payload portions of multiple frames are identified and extracted. These payloads are switched and re-mapped to a different STM structure as required.

Abstract translation: 接收到多帧SDH帧数据。 每个帧具有开销部分和有效载荷部分。 识别并提取多个帧的有效载荷部分。 这些有效载荷被切换并根据需要重新映射到不同的STM结构。

公开(公告)号：US08179887B1

公开(公告)日：2012-05-15

申请号：US12024806

申请日：2008-02-01

Applicant: Naveen K. Jain ,  Venkata Rangavajjhala

Inventor： Naveen K. Jain ,  Venkata Rangavajjhala

IPC: H04Q11/04

CPC classification number: H04Q11/04 ,  H04L45/00

Abstract: A network system, having an array of processing engines (“PEs”) and a delay line, improves packet processing performance for time division multiplexing (“TDM”) sequencing of PEs. The system includes an ingress circuit, a delay line, a demultiplexer, a tag memory, and a multiplexer. After the ingress circuit receives a packet from an input port, the delay line stores the packet together with a unique tag value. The delay line, in one embodiment, provides a predefined time delay for the packet. Once the demultiplexer forwards the packet to an array of PEs for packet processing, a tag memory stores the tag value indexed by PE number. The PE number identifies a PE in the array, which was assigned to process the packet. The multiplexer is capable of multiplex packets from PE array and replacing the packet with the processed packet in the delay line in response to the tag value.

Abstract translation: 具有处理引擎（“PE”）和延迟线阵列的网络系统提高了PE的时分复用（“TDM”）排序的分组处理性能。 该系统包括入口电路，延迟线，解复用器，标签存储器和多路复用器。 在入口电路从输入端口接收到数据包之后，延迟线将数据包与唯一的标签值一起存储。 在一个实施例中，延迟线为分组提供预定义的时间延迟。 一旦解复用器将分组转发到用于分组处理的PE阵列，则标签存储器存储由PE号索引的标签值。 PE号码标识阵列中的一个PE，分配给该数据包进行处理。 多路复用器能够对来自PE阵列的数据包进行复用，并响应于标签值，在延迟线中用处理后的数据包替换数据包。

公开(公告)号：US07855967B1

公开(公告)日：2010-12-21

申请号：US12239041

申请日：2008-09-26

Applicant: Venkata Rangavajjhala ,  Marc A. Schaub

Inventor： Venkata Rangavajjhala ,  Marc A. Schaub

IPC: H04J1/16 ,  H04J3/14 ,  G06F13/28 ,  G06F15/173

CPC classification number: H04L43/026 ,  H04L43/14

Abstract: An apparatus and method for using a direct memory access (“DMA”) to facilitate netflow statistics are disclosed. A network device such as a router or a switch, in one embodiment, includes a statistic component, a local memory, and a memory access controller. The statistic component is configured to gather information relating to net usage from packet flows or netflows in response to corresponding index values or tags. While the local memory such as a cache provides the index values or tags assignable to packet flows, the memory access controller such as a DMA transfers at least a portion of the index values or tags between the local memory and a main memory for enhancing capacity of the local memory.

Abstract translation: 公开了一种使用直接存储器访问（“DMA”）来促进净流统计的装置和方法。 在一个实施例中，诸如路由器或交换机的网络设备包括统计组件，本地存储器和存储器访问控制器。 统计组件被配置为响应于相应的索引值或标签从分组流或网络流收集与净使用有关的信息。 虽然诸如高速缓存的本地存储器提供可分配给分组流的索引值或标签，但诸如DMA之类的存储器访问控制器传送本地存储器和主存储器之间的索引值或标签的至少一部分，以增强 本地记忆。

公开(公告)号：US08811410B1

公开(公告)日：2014-08-19

申请号：US13531272

申请日：2012-06-22

Applicant: Naveen K. Jain ,  Venkata Rangavajjhala

Inventor： Naveen K. Jain ,  Venkata Rangavajjhala

IPC: H04L12/28

CPC classification number: H04L47/28 ,  H04J3/0682 ,  H04L45/74

Abstract: A network device having a system performance measurement unit employing one or more global time stamps for measuring the device performance is disclosed. The device includes an ingress circuit, a global time counter, an egress circuit, and a processor. The ingress circuit is configured to receive a packet from an input port while the global time counter generates an arrival time stamp in accordance with the arrival time of the packet. The egress circuit is capable of forwarding the packet to other network devices via an output port. The processor, in one embodiment, is configured to calculate packet latency in response to the arrival time stamp.

Abstract translation: 公开了一种具有系统性能测量单元的网络设备，该单元采用一个或多个全局时间戳来测量设备性能。 该设备包括入口电路，全局时间计数器，出口电路和处理器。 入口电路被配置为在全局时间计数器根据分组的到达时间产生到达时间戳时从输入端口接收分组。 出口电路能够通过输出端口将数据包转发到其他网络设备。 在一个实施例中，处理器被配置为响应于到达时间戳来计算分组等待时间。

公开(公告)号：US07796062B1

公开(公告)日：2010-09-14

申请号：US11874077

申请日：2007-10-17

Applicant: Venkata Rangavajjhala ,  Naveen K. Jain

Inventor： Venkata Rangavajjhala ,  Naveen K. Jain

IPC: H03M7/16

CPC classification number: H03M7/16

Abstract: An apparatus and a method for enhancing digital processing implementation using non-power-of-two even count Gray coding are disclosed. The even count encoding device includes a first circuit, a second circuit, and a coding circuit. The first circuit, in one embodiment, is configured to identify a first portion of entries in a table in response to an input number. The second circuit is capable of determining a second portion of entries in the table in response to the input number, wherein the number of the first portion of entries and the number of the second portion of the entries are substantially the same. The coding circuit is operable to concatenate the second portion of the entries to the first portion of the entries to form an output table, which includes a sequence of even count integers wherein the difference between two adjacent integers is one bit position.

Abstract translation: 公开了一种使用非二次偶数灰度编码来增强数字处理实现的装置和方法。 偶数编码装置包括第一电路，第二电路和编码电路。 在一个实施例中，第一电路被配置为响应于输入号码来识别表中的条目的第一部分。 第二电路能够响应于输入号码确定表中的条目的第二部分，其中条目的第一部分的数量和条目的第二部分的数量基本相同。 编码电路可操作以将条目的第二部分连接到条目的第一部分以形成输出表，其包括偶数计数整数序列，其中两个相邻整数之间的差是一位位置。

公开(公告)号：US08169915B1

公开(公告)日：2012-05-01

申请号：US12239118

申请日：2008-09-26

Applicant: Venkata Rangavajjhala ,  Marc A. Schaub

Inventor： Venkata Rangavajjhala ,  Marc A. Schaub

IPC: H04J1/16

CPC classification number: H04L45/125 ,  H04L45/7453

Abstract: An apparatus and a method for load balancing across multiple routes using an indirection table and hash function during a process of packet classification are disclosed. A network device such as a router includes a memory, a hash component, and a result memory. The memory is referred to as an indirection random access memory (“RAM”), is capable of storing information regarding number of paths from source devices to destination devices. The memory, in one embodiment, provides a base index value and a range number indicating the number of paths associated with the base index value. The hash component generates a hash index in response to the base index value and the range number. Upon generation of hash index, the result memory identifies a classification result in response to the hash index.

Abstract translation: 公开了一种在分组过程中使用间接表和散列函数在多个路由之间进行负载平衡的装置和方法。 诸如路由器的网络设备包括存储器，散列组件和结果存储器。 存储器被称为间接随机存取存储器（“RAM”），能够存储关于从源设备到目的地设备的路径数量的信息。 在一个实施例中，存储器提供基本索引值和指示与基本索引值相关联的路径的数量的范围号。 哈希组件响应于基本索引值和范围数量生成哈希索引。 在生成散列索引时，结果存储器响应于散列索引识别分类结果。

公开(公告)号：US20120076140A1

公开(公告)日：2012-03-29

申请号：US13289652

申请日：2011-11-04

Applicant: Naveen K. Jain ,  Venkata Rangavajjhala

Inventor： Naveen K. Jain ,  Venkata Rangavajjhala

IPC: H04L12/56

CPC classification number: H04L49/3036 ,  H04L49/103 ,  H04L49/3063

Abstract: A network processing device having multiple processing engines capable of providing multi-context parallel processing is disclosed. The device includes a receiver and a packet processor, wherein the receiver is capable of receiving packets at a predefined packet flow rate. The packet processor, in one embodiment, includes multiple processing engines, wherein each processing engine is further configured to include multiple context processing components. The context processing components are used to provide multi-context parallel processing to increase throughput.

Abstract translation: 公开了具有能够提供多上下文并行处理的多个处理引擎的网络处理装置。 该设备包括接收机和分组处理器，其中接收机能够以预定的分组流速接收分组。 在一个实施例中，分组处理器包括多个处理引擎，其中每个处理引擎还被配置为包括多个上下文处理组件。 上下文处理组件用于提供多上下文并行处理以增加吞吐量。

公开(公告)号：US08074054B1

公开(公告)日：2011-12-06

申请号：US11954718

申请日：2007-12-12

Applicant: Venkata Rangavajjhala ,  Naveen K. Jain

Inventor： Venkata Rangavajjhala ,  Naveen K. Jain

IPC: G06F15/00 ,  G06F15/76

CPC classification number: G06F15/8015

Abstract: A processing system includes a group of processing units (“PUs”) arranged in a daisy chain configuration or a sequence capable of parallel processing. The processing system, in one embodiment, includes PUs, a demultiplexer (“demux”), and a multiplexer (“mux”). The PUs are connected or linked in a sequence or a daisy chain configuration wherein a first PU is located at the beginning of the sequence and a last digital PU is located at the end of the sequence. Each PU is configured to read an input data packet from a packet stream during a designated reading time frame. If the time frame is outside of the designated reading time frame, a PU allows a packet stream to pass through. The demux forwards a packet stream to the first digital processing unit. The mux receives a packet steam from the last digital processing unit.

Abstract translation: 处理系统包括以菊花链配置布置的一组处理单元（“PU”）或能够并行处理的序列。 在一个实施例中，处理系统包括PU，解复用器（“demux”）和多路复用器（“多路复用器”）。 PU以序列或菊花链配置连接或链接，其中第一PU位于序列的开始处，并且最后的数字PU位于序列的末尾。 每个PU被配置为在指定的读取时间帧期间从分组流读取输入数据分组。 如果时间帧在指定的读取时间帧之外，则PU允许分组流通过。 解复用器将分组流转发到第一数字处理单元。 多路复用器从最后一个数字处理单元接收数据包流。

公开(公告)号：US09559987B1

公开(公告)日：2017-01-31

申请号：US12239084

申请日：2008-09-26

Applicant: Venkata Rangavajjhala ,  Marc A. Schaub

Inventor： Venkata Rangavajjhala ,  Marc A. Schaub

IPC: H04L12/28 ,  G06F13/28 ,  H04L12/935 ,  G11C15/00

CPC classification number: H04L49/3009 ,  G11C15/00 ,  H04L45/742 ,  H04L45/7457

Abstract: An apparatus and method of using a cache to improve a learn rate for a content-addressable memory (“CAM”) are disclosed. A network device such as a router or a switch, in one embodiment, includes a key generator, a searching circuit, and a key cache, wherein the key generator is capable of generating a first lookup key in response to a first packet. The searching circuit is configured to search the content of the CAM to match the first lookup key. If the first lookup key is not found in the CAM, the key cache stores the first lookup key in response to a first miss.

Abstract translation: 公开了一种使用高速缓存来提高内容寻址存储器（“CAM”）的学习率的装置和方法。 在一个实施例中，诸如路由器或交换机的网络设备包括密钥生成器，搜索电路和密钥高速缓存，其中密钥生成器能够响应于第一数据包生成第一查找密钥。 搜索电路被配置为搜索CAM的内容以匹配第一查找密钥。 如果在CAM中没有找到第一个查找密钥，则密钥缓存存储响应于第一个缺失的第一查找密钥。