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公开(公告)号：US08201067B2
公开(公告)日：2012-06-12
申请号：US12037038
申请日：2008-02-25
CPC分类号： G06F11/10
摘要： A method for processor error checking including receiving an instruction data, generating a pre-processing parity data based on the instruction data, maintaining the pre-processing parity data, processing the instruction data, generating a post-processing parity data based on the processed instruction data, checking for an error related to processing the instruction data by comparing the post-processing parity data to the pre-processing parity data, and transmitting an error signal that indicates the error related to processing the instruction data occurred if the post-processing parity data does not match the pre-processing parity data, wherein checking for the error related to processing the instruction data is performed without using a duplicate processing circuitry.
摘要翻译： 一种用于处理器错误检查的方法，包括接收指令数据，基于指令数据产生预处理奇偶校验数据，维持预处理奇偶校验数据，处理指令数据，基于处理指令产生后处理奇偶校验数据 数据，通过将后处理奇偶校验数据与预处理奇偶校验数据进行比较来检查与处理指令数据相关的错误，以及如果后处理奇偶校验数据发送指示与处理指令数据相关的错误的错误信号 数据与预处理奇偶校验数据不匹配，其中在不使用重复处理电路的情况下执行检查与处理指令数据有关的错误。
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2.发明申请METHOD, SYSTEM, AND COMPUTER PROGRAM PRODUCT FOR PROCESSOR ERROR CHECKING 有权用于处理器错误检查的方法，系统和计算机程序产品公开(公告)号：US20090217077A1
公开(公告)日：2009-08-27
申请号：US12037038
申请日：2008-02-25
IPC分类号： G06F11/07
CPC分类号： G06F11/10
摘要： A method for processor error checking including receiving an instruction data, generating a pre-processing parity data based on the instruction data, maintaining the pre-processing parity data, processing the instruction data, generating a post-processing parity data based on the processed instruction data, checking for an error related to processing the instruction data by comparing the post-processing parity data to the pre-processing parity data, and transmitting an error signal that indicates the error related to processing the instruction data occurred if the post-processing parity data does not match the pre-processing parity data, wherein checking for the error related to processing the instruction data is performed without using a duplicate processing circuitry.
摘要翻译： 一种用于处理器错误检查的方法，包括接收指令数据，基于指令数据产生预处理奇偶校验数据，维持预处理奇偶校验数据，处理指令数据，基于处理指令产生后处理奇偶校验数据 数据，通过将后处理奇偶校验数据与预处理奇偶校验数据进行比较来检查与处理指令数据相关的错误，以及如果后处理奇偶校验数据发送指示与处理指令数据相关的错误的错误信号 数据与预处理奇偶校验数据不匹配，其中在不使用重复处理电路的情况下执行检查与处理指令数据有关的错误。
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3.发明申请METHOD, SYSTEM AND COMPUTER PROGRAM PRODUCT FOR SUPPORTING PARTIAL RECYCLE IN A PIPELINED MICROPROCESSOR 有权用于支持管道微处理器部分回收的方法，系统和计算机程序产品公开(公告)号：US20090240921A1
公开(公告)日：2009-09-24
申请号：US12051486
申请日：2008-03-19
IPC分类号： G06F9/30
CPC分类号： G06F9/3865 , G06F9/3836 , G06F9/3842
摘要： A computer processing system is provided. The computer processing system includes a first datastore that stores a subset of information associated with an instruction. A first stage of a processor pipeline writes the subset of information to the first datastore based on an execution of an operation associated with the instruction. A second stage of the pipeline initiates reprocessing of the operation associated with the instruction based on the subset of information stored in the first datastore.
摘要翻译： 提供了一种计算机处理系统。 计算机处理系统包括存储与指令相关联的信息的子集的第一数据存储区。 处理器流水线的第一阶段基于与指令相关联的操作的执行将信息子集写入第一数据存储区。 管道的第二阶段基于存储在第一数据存储区中的信息子集来启动与指令相关联的操作的再处理。
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公开(公告)号：US08516228B2
公开(公告)日：2013-08-20
申请号：US12051486
申请日：2008-03-19
IPC分类号： G06F9/00
CPC分类号： G06F9/3865 , G06F9/3836 , G06F9/3842
摘要： A computer processing system is provided. The computer processing system includes a first datastore that stores a subset of information associated with an instruction. A first stage of a processor pipeline writes the subset of information to the first datastore based on an execution of an operation associated with the instruction. A second stage of the pipeline initiates reprocessing of the operation associated with the instruction based on the subset of information stored in the first datastore.
摘要翻译： 提供了一种计算机处理系统。 计算机处理系统包括存储与指令相关联的信息的子集的第一数据存储区。 处理器流水线的第一阶段基于与指令相关联的操作的执行将信息子集写入第一数据存储区。 管道的第二阶段基于存储在第一数据存储区中的信息子集来启动与指令相关联的操作的再处理。
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5.发明授权Processor and method for synchronous load multiple fetching sequence and pipeline stage result tracking to facilitate early address generation interlock bypass 失效处理器和方法用于同步加载多个提取序列和流水线阶段结果跟踪，以促进早期地址生成互锁旁路公开(公告)号：US07987343B2
公开(公告)日：2011-07-26
申请号：US12051527
申请日：2008-03-19
CPC分类号： G06F9/3867 , G06F9/30043 , G06F9/3826 , G06F9/3838 , G06F9/3857
摘要： A pipelined processor including an architecture for address generation interlocking, the processor including: an instruction grouping unit to detect a read-after-write dependency and to resolve instruction interdependency; an instruction dispatch unit (IDU) including address generation interlock (AGI) and operand fetching logic for dispatching an instruction to at least one of a load store unit and an execution unit; wherein the load store unit is configured with access to a data cache and to return fetched data to the execution unit; wherein the execution unit is configured to write data into a general purpose register bank; and wherein the architecture provides support for bypassing of results of a load multiple instruction for address generation while such instruction is executing in the execution unit before the general purpose register bank is written. A method and a computer system are also provided.
摘要翻译： 一种流水线处理器，包括用于地址生成互锁的架构，所述处理器包括：指令分组单元，用于检测写后依赖关系并解决指令相互依赖性; 指令分配单元（IDU），包括地址生成互锁（AGI）和操作数提取逻辑，用于向至少一个加载存储单元和执行单元分发指令; 其中所述加载存储单元被配置为访问数据高速缓存并且将获取的数据返回到所述执行单元; 其中所述执行单元被配置为将数据写入通用寄存器组; 并且其中所述体系结构提供了对在写入通用寄存器组之前在执行单元中执行这种指令的地址生成的负载多重指令的结果的旁路支持。 还提供了一种方法和计算机系统。
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公开(公告)号：US20090240914A1
公开(公告)日：2009-09-24
申请号：US12051215
申请日：2008-03-19
申请人： Edward T. Malley , Khary J. Alexander , Fadi Y. Busaba , Vimal M. Kapadia , Jeffrey S. Plate , John G. Rell, JR. , Chung-Lung Kevin Shum
发明人： Edward T. Malley , Khary J. Alexander , Fadi Y. Busaba , Vimal M. Kapadia , Jeffrey S. Plate , John G. Rell, JR. , Chung-Lung Kevin Shum
IPC分类号： G06F9/38
CPC分类号： G06F9/30065 , G06F9/3832
摘要： A pipelined microprocessor configured for long operand instructions is disclosed. The microprocessor includes a memory unit and a load-store unit. The load store unit is coupled to the memory unit and includes a data formatter receiving information from the memory unit and including an operand selector and a shift register portion. The microprocessor also includes an execution unit coupled to the load-store unit and receiving operand information there from. The execution unit includes output latches coupled to a storage location within the execution unit for storing output information from the execution unit.
摘要翻译： 公开了配置用于长操作数指令的流水线微处理器。 微处理器包括存储单元和加载存储单元。 加载存储单元耦合到存储器单元，并且包括从存储器单元接收信息并包括操作数选择器和移位寄存器部分的数据格式化器。 微处理器还包括耦合到加载存储单元并从其接收操作数信息的执行单元。 执行单元包括耦合到执行单元内的存储位置的输出锁存器，用于存储来自执行单元的输出信息。
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7.发明申请PROCESSOR AND METHOD FOR SYNCHRONOUS LOAD MULTIPLE FETCHING SEQUENCE AND PIPELINE STAGE RESULT TRACKING TO FACILITATE EARLY ADDRESS GENERATION INTERLOCK BYPASS 失效同步负载多处理电路序列和管道阶段结果跟踪的处理器和方法来简化地址生成间接旁路公开(公告)号：US20090240919A1
公开(公告)日：2009-09-24
申请号：US12051527
申请日：2008-03-19
IPC分类号： G06F9/312
CPC分类号： G06F9/3867 , G06F9/30043 , G06F9/3826 , G06F9/3838 , G06F9/3857
摘要： A pipelined processor including an architecture for address generation interlocking, the processor including: an instruction grouping unit to detect a read-after-write dependency and to resolve instruction interdependency; an instruction dispatch unit (IDU) including address generation interlock (AGI) and operand fetching logic for dispatching an instruction to at least one of a load store unit and an execution unit; wherein the load store unit is configured with access to a data cache and to return fetched data to the execution unit; wherein the execution unit is configured to write data into a general purpose register bank; and wherein the architecture provides support for bypassing of results of a load multiple instruction for address generation while such instruction is executing in the execution unit before the general purpose register bank is written. A method and a computer system are also provided.
摘要翻译： 一种流水线处理器，包括用于地址生成互锁的架构，所述处理器包括：指令分组单元，用于检测写后依赖关系并解决指令相互依赖性; 指令分配单元（IDU），包括地址生成互锁（AGI）和操作数提取逻辑，用于向至少一个加载存储单元和执行单元分发指令; 其中所述加载存储单元被配置为访问数据高速缓存并且将获取的数据返回到所述执行单元; 其中所述执行单元被配置为将数据写入通用寄存器组; 并且其中所述体系结构提供了对在写入通用寄存器组之前在执行单元中执行这种指令的地址生成的负载多重指令的结果的旁路支持。 还提供了一种方法和计算机系统。
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公开(公告)号：US07962726B2
公开(公告)日：2011-06-14
申请号：US12051215
申请日：2008-03-19
申请人： Edward T. Malley , Khary J. Alexander , Fadi Y. Busaba , Vimal M. Kapadia , Jeffrey S. Plate , John G. Rell, Jr. , Chung-Lung Kevin Shum
发明人： Edward T. Malley , Khary J. Alexander , Fadi Y. Busaba , Vimal M. Kapadia , Jeffrey S. Plate , John G. Rell, Jr. , Chung-Lung Kevin Shum
CPC分类号： G06F9/30065 , G06F9/3832
摘要： A pipelined microprocessor configured for long operand instructions is disclosed. The microprocessor includes a memory unit and a load-store unit. The load store unit is coupled to the memory unit and includes a data formatter receiving information from the memory unit and including an operand selector and a shift register portion. The microprocessor also includes an execution unit coupled to the load-store unit and receiving operand information there from. The execution unit includes output latches coupled to a storage location within the execution unit for storing output information from the execution unit.
摘要翻译： 公开了配置用于长操作数指令的流水线微处理器。 微处理器包括存储单元和加载存储单元。 加载存储单元耦合到存储器单元，并且包括从存储器单元接收信息并包括操作数选择器和移位寄存器部分的数据格式化器。 微处理器还包括耦合到加载存储单元并从其接收操作数信息的执行单元。 执行单元包括耦合到执行单元内的存储位置的输出锁存器，用于存储来自执行单元的输出信息。
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9.发明授权Facilitating processing in a computing environment using an extended drain instruction 有权在计算环境中利用扩展的漏极指令促进处理公开(公告)号：US08078843B2
公开(公告)日：2011-12-13
申请号：US12023155
申请日：2008-01-31
申请人： Khary J. Alexander , Fadi Y. Busaba , Mark S. Farrell , Bruce C. Giamei , Timothy J. Slegel , Charles F. Webb
发明人： Khary J. Alexander , Fadi Y. Busaba , Mark S. Farrell , Bruce C. Giamei , Timothy J. Slegel , Charles F. Webb
IPC分类号： G06F9/30
CPC分类号： G06F9/30079 , G06F9/30145 , G06F9/3867
摘要： An extended DRAIN instruction is used to stall processing within a computing environment. The instruction includes an indication of the one or more processing stages at which processing is to be stalled. It also includes a control that allows processing to be stalled for additional cycles, as desired. The enhanced DRAIN instruction enables its use to be more granular and to have minimal impact with respect to each individual use.
摘要翻译： 扩展DRAIN指令用于在计算环境中停止处理。 该指令包括处理被停止的一个或多个处理阶段的指示。 它还包括一个控制，允许根据需要使处理停滞在额外的周期。 增强的DRAIN指令使其使用更细致，对每个用户的影响最小。
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10.发明授权Method, system, and computer program product for selectively accelerating early instruction processing 失效方法，系统和计算机程序产品，用于选择性加速早期指令处理公开(公告)号：US07861064B2
公开(公告)日：2010-12-28
申请号：US12037861
申请日：2008-02-26
申请人： Khary J. Alexander , Fadi Y. Busaba , Bruce C. Giamei , David S. Hutton , Chung-Lung Kevin Shum
发明人： Khary J. Alexander , Fadi Y. Busaba , Bruce C. Giamei , David S. Hutton , Chung-Lung Kevin Shum
CPC分类号： G06F9/3826 , G06F9/3836
摘要： A method for selectively accelerating early instruction processing including receiving an instruction data that is normally processed in an execution stage of a processor pipeline, wherein a configuration of the instruction data allows a processing of the instruction data to be accelerated from the execution stage to an address generation stage that occurs earlier in the processor pipeline than the execution stage, determining whether the instruction data can be dispatched to the address generation stage to be processed without being delayed due to an unavailability of a processing resource needed for the processing of the instruction data in the address generation stage, dispatching the instruction data to be processed in the address generation stage if it can be dispatched without being delayed due to the unavailability of the processing resource, and dispatching the instruction data to be processed in the execution stage if it can not be dispatched without being delayed due to the unavailability of the processing resource, wherein the processing of the instruction data is selectively accelerated using an address generation interlock scheme. A corresponding system and computer program product.
摘要翻译： 一种用于选择性地加速早期指令处理的方法，包括接收在处理器流水线的执行阶段中正常处理的指令数据，其中指令数据的配置允许指令数据的处理从执行阶段加速到地址 在处理器流水线中比执行阶段更早发生的生成阶段，确定指令数据是否可以被分派到要处理的地址生成阶段，而不会由于处理指令数据所需的处理资源的不可用而被延迟 地址生成阶段，如果能够由于处理资源的不可用而被分派而不被延迟，则在地址生成阶段调度要处理的指令数据，并且如果不能在执行阶段调度要处理的指令数据 由于你而不被推迟 处理资源的可用性，其中使用地址生成互锁方案选择性地加速指令数据的处理。 相应的系统和计算机程序产品。
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