公开(公告)号：US20090240918A1

公开(公告)日：2009-09-24

申请号：US12051296

申请日：2008-03-19

申请人： Vimal M. Kapadia ,  Fadi Y. Busaba ,  Edward T. Malley ,  John G. Rell, JR. ,  Chung-Lung Kevin Shum

发明人： Vimal M. Kapadia ,  Fadi Y. Busaba ,  Edward T. Malley ,  John G. Rell, JR. ,  Chung-Lung Kevin Shum

IPC分类号： G06F9/30

CPC分类号： G06F9/3824

摘要： Eliminating or reducing an operand line crossing penalty by performing an initial fetch for an operand from a data cache of a processor. The initial fetch is performed by allowing or permitting the initial fetch to occur unaligned with reference to a quadword boundary. A plurality of subsequent fetches for a corresponding plurality of operands from the data cache are performed wherein each of the plurality of subsequent fetches is aligned to any of a plurality of quadword boundaries to prevent each of a plurality of individual fetch requests from spanning a plurality of lines in the data cache. A steady stream of data is maintained by placing an operand buffer at an output of the data cache to store and merge data from the initial fetch and the plurality of subsequent fetches, and to return the stored and merged data to the processor.

摘要翻译： 通过从处理器的数据高速缓存中执行对操作数的初始提取来消除或减少操作数线路交叉处罚。 初始提取是通过允许或允许以参考四字边界未对齐的方式发生初始提取而执行的。 执行用于来自数据高速缓存的相应多个操作数的多个后续提取，其中多个后续提取中的每一个与多个四字边界中的任何一个对齐，以防止多个单独提取请求中的每一个跨越多个 数据缓存中的行。 通过在数据高速缓存的输出处放置操作数缓冲器来存储和合并来自初始提取和多个后续提取的数据并将存储和合并的数据返回到处理器来维持稳定的数据流。

公开(公告)号：US09201655B2

公开(公告)日：2015-12-01

申请号：US12051296

申请日：2008-03-19

申请人： Vimal M. Kapadia ,  Fadi Y. Busaba ,  Edward T. Malley ,  John G. Rell, Jr. ,  Chung-Lung Kevin Shum

发明人： Vimal M. Kapadia ,  Fadi Y. Busaba ,  Edward T. Malley ,  John G. Rell, Jr. ,  Chung-Lung Kevin Shum

IPC分类号： G06F13/00 ,  G06F13/28 ,  G06F9/38

CPC分类号： G06F9/3824

摘要： Eliminating or reducing an operand line crossing penalty by performing an initial fetch for an operand from a data cache of a processor. The initial fetch is performed by allowing or permitting the initial fetch to occur unaligned with reference to a quadword boundary. A plurality of subsequent fetches for a corresponding plurality of operands from the data cache are performed wherein each of the plurality of subsequent fetches is aligned to any of a plurality of quadword boundaries to prevent each of a plurality of individual fetch requests from spanning a plurality of lines in the data cache. A steady stream of data is maintained by placing an operand buffer at an output of the data cache to store and merge data from the initial fetch and the plurality of subsequent fetches, and to return the stored and merged data to the processor.

摘要翻译： 通过从处理器的数据高速缓存中执行对操作数的初始提取来消除或减少操作数线路交叉处罚。 初始提取是通过允许或允许以参考四字边界未对齐的方式发生初始提取而执行的。 执行用于来自数据高速缓存的相应多个操作数的多个后续提取，其中多个后续提取中的每一个与多个四字边界中的任何一个对齐，以防止多个单独提取请求中的每一个跨越多个 数据缓存中的行。 通过在数据高速缓存的输出处放置操作数缓冲器来存储和合并来自初始提取和多个后续提取的数据并将存储和合并的数据返回到处理器来维持稳定的数据流。

公开(公告)号：US07962726B2

公开(公告)日：2011-06-14

申请号：US12051215

申请日：2008-03-19

申请人： Edward T. Malley ,  Khary J. Alexander ,  Fadi Y. Busaba ,  Vimal M. Kapadia ,  Jeffrey S. Plate ,  John G. Rell, Jr. ,  Chung-Lung Kevin Shum

发明人： Edward T. Malley ,  Khary J. Alexander ,  Fadi Y. Busaba ,  Vimal M. Kapadia ,  Jeffrey S. Plate ,  John G. Rell, Jr. ,  Chung-Lung Kevin Shum

IPC分类号： G06F9/00 ,  G06F9/44

CPC分类号： G06F9/30065 ,  G06F9/3832

摘要： A pipelined microprocessor configured for long operand instructions is disclosed. The microprocessor includes a memory unit and a load-store unit. The load store unit is coupled to the memory unit and includes a data formatter receiving information from the memory unit and including an operand selector and a shift register portion. The microprocessor also includes an execution unit coupled to the load-store unit and receiving operand information there from. The execution unit includes output latches coupled to a storage location within the execution unit for storing output information from the execution unit.

摘要翻译： 公开了配置用于长操作数指令的流水线微处理器。 微处理器包括存储单元和加载存储单元。 加载存储单元耦合到存储器单元，并且包括从存储器单元接收信息并包括操作数选择器和移位寄存器部分的数据格式化器。 微处理器还包括耦合到加载存储单元并从其接收操作数信息的执行单元。 执行单元包括耦合到执行单元内的存储位置的输出锁存器，用于存储来自执行单元的输出信息。

公开(公告)号：US20090240914A1

公开(公告)日：2009-09-24

申请号：US12051215

申请日：2008-03-19

申请人： Edward T. Malley ,  Khary J. Alexander ,  Fadi Y. Busaba ,  Vimal M. Kapadia ,  Jeffrey S. Plate ,  John G. Rell, JR. ,  Chung-Lung Kevin Shum

发明人： Edward T. Malley ,  Khary J. Alexander ,  Fadi Y. Busaba ,  Vimal M. Kapadia ,  Jeffrey S. Plate ,  John G. Rell, JR. ,  Chung-Lung Kevin Shum

IPC分类号： G06F9/38

CPC分类号： G06F9/30065 ,  G06F9/3832

摘要： A pipelined microprocessor configured for long operand instructions is disclosed. The microprocessor includes a memory unit and a load-store unit. The load store unit is coupled to the memory unit and includes a data formatter receiving information from the memory unit and including an operand selector and a shift register portion. The microprocessor also includes an execution unit coupled to the load-store unit and receiving operand information there from. The execution unit includes output latches coupled to a storage location within the execution unit for storing output information from the execution unit.

摘要翻译： 公开了配置用于长操作数指令的流水线微处理器。 微处理器包括存储单元和加载存储单元。 加载存储单元耦合到存储器单元，并且包括从存储器单元接收信息并包括操作数选择器和移位寄存器部分的数据格式化器。 微处理器还包括耦合到加载存储单元并从其接收操作数信息的执行单元。 执行单元包括耦合到执行单元内的存储位置的输出锁存器，用于存储来自执行单元的输出信息。

公开(公告)号：US20090240922A1

公开(公告)日：2009-09-24

申请号：US12051792

申请日：2008-03-19

申请人： David S. Hutton ,  Fadi Y. Busaba ,  Bruce C. Giamei ,  Christopher A. Krygowski ,  Edward T. Malley ,  Jeffrey S. Plate ,  John G. Rell, JR. ,  Chung-Lung Kevin Shum ,  Timothy J. Slegel

发明人： David S. Hutton ,  Fadi Y. Busaba ,  Bruce C. Giamei ,  Christopher A. Krygowski ,  Edward T. Malley ,  Jeffrey S. Plate ,  John G. Rell, JR. ,  Chung-Lung Kevin Shum ,  Timothy J. Slegel

IPC分类号： G06F9/30

CPC分类号： G06F9/3016 ,  G06F9/30036 ,  G06F9/3828

摘要： Result and operand forwarding is provided between differently sized operands in a superscalar processor by grouping a first set of instructions for operand forwarding, and grouping a second set of instructions for result forwarding, the first set of instructions comprising a first source instruction having a first operand and a first dependent instruction having a second operand, the first dependent instruction depending from the first source instruction; the second set of instructions comprising a second source instruction having a third operand and a second dependent instruction having a fourth operand, the second dependent instruction depending from the second source instruction, performing operand forwarding by forwarding the first operand, either whole or in part, as it is being read to the first dependent instruction prior to execution; performing result forwarding by forwarding a result of the second source instruction, either whole or in part, to the second dependent instruction, after execution; wherein the operand forwarding is performed by executing the first source instruction together with the first dependent instruction; and wherein the result forwarding is performed by executing the second source instruction together with the second dependent instruction.

摘要翻译： 通过对用于操作数转发的第一组指令进行分组，以及对用于结果转发的第二组指令进行分组，在超标量处理器中的不同大小的操作数之间提供结果和操作数转发，所述第一组指令包括具有第一操作数的第一源指令 以及具有第二操作数的第一依赖指令，所述第一依赖指令取决于所述第一源指令; 所述第二组指令包括具有第三操作数和第二从属指令的第二源指令，所述第三操作数和第二从属指令具有第四操作数，所述第二依赖指令取决于所述第二源指令，通过转发所述第一操作数全部或部分地执行操作数转发， 因为它在执行之前被读取到第一个依赖指令; 执行结果转发，将第二源指令的结果全部或部分转发到第二依赖指令; 其中通过与第一依赖指令一起执行第一源指令来执行操作数转发; 并且其中通过与第二从属指令一起执行第二源指令来执行结果转发。

公开(公告)号：US07921279B2

公开(公告)日：2011-04-05

申请号：US12051792

申请日：2008-03-19

申请人： David S. Hutton ,  Fadi Y. Busaba ,  Bruce C. Giamei ,  Christopher A. Krygowski ,  Edward T. Malley ,  Jeffrey S. Plate ,  John G. Rell, Jr. ,  Chung-Lung Kevin Shum ,  Timothy J. Slegel

发明人： David S. Hutton ,  Fadi Y. Busaba ,  Bruce C. Giamei ,  Christopher A. Krygowski ,  Edward T. Malley ,  Jeffrey S. Plate ,  John G. Rell, Jr. ,  Chung-Lung Kevin Shum ,  Timothy J. Slegel

IPC分类号： G06F9/30

CPC分类号： G06F9/3016 ,  G06F9/30036 ,  G06F9/3828

摘要： Result and operand forwarding is provided between differently sized operands in a superscalar processor by grouping a first set of instructions for operand forwarding, and grouping a second set of instructions for result forwarding, the first set of instructions comprising a first source instruction having a first operand and a first dependent instruction having a second operand, the first dependent instruction depending from the first source instruction; the second set of instructions comprising a second source instruction having a third operand and a second dependent instruction having a fourth operand, the second dependent instruction depending from the second source instruction, performing operand forwarding by forwarding the first operand, either whole or in part, as it is being read to the first dependent instruction prior to execution; performing result forwarding by forwarding a result of the second source instruction, either whole or in part, to the second dependent instruction, after execution; wherein the operand forwarding is performed by executing the first source instruction together with the first dependent instruction; and wherein the result forwarding is performed by executing the second source instruction together with the second dependent instruction.

摘要翻译： 通过对用于操作数转发的第一组指令进行分组，以及对用于结果转发的第二组指令进行分组，在超标量处理器中的不同大小的操作数之间提供结果和操作数转发，所述第一组指令包括具有第一操作数的第一源指令 以及具有第二操作数的第一依赖指令，所述第一依赖指令取决于所述第一源指令; 所述第二组指令包括具有第三操作数和第二从属指令的第二源指令，所述第三操作数和第二从属指令具有第四操作数，所述第二依赖指令取决于所述第二源指令，通过转发所述第一操作数全部或部分地执行操作数转发， 因为它在执行之前被读取到第一个依赖指令; 执行结果转发，将第二源指令的结果全部或部分转发到第二依赖指令; 其中通过与第一依赖指令一起执行第一源指令来执行操作数转发; 并且其中通过与第二从属指令一起执行第二源指令来执行结果转发。

公开(公告)号：US20090240919A1

公开(公告)日：2009-09-24

申请号：US12051527

申请日：2008-03-19

申请人： Khary J. Alexander ,  Fadi Y. Busaba ,  Vimal M. Kapadia ,  Chung-Lung Kevin Shum

发明人： Khary J. Alexander ,  Fadi Y. Busaba ,  Vimal M. Kapadia ,  Chung-Lung Kevin Shum

IPC分类号： G06F9/312

CPC分类号： G06F9/3867 ,  G06F9/30043 ,  G06F9/3826 ,  G06F9/3838 ,  G06F9/3857

摘要： A pipelined processor including an architecture for address generation interlocking, the processor including: an instruction grouping unit to detect a read-after-write dependency and to resolve instruction interdependency; an instruction dispatch unit (IDU) including address generation interlock (AGI) and operand fetching logic for dispatching an instruction to at least one of a load store unit and an execution unit; wherein the load store unit is configured with access to a data cache and to return fetched data to the execution unit; wherein the execution unit is configured to write data into a general purpose register bank; and wherein the architecture provides support for bypassing of results of a load multiple instruction for address generation while such instruction is executing in the execution unit before the general purpose register bank is written. A method and a computer system are also provided.

摘要翻译： 一种流水线处理器，包括用于地址生成互锁的架构，所述处理器包括：指令分组单元，用于检测写后依赖关系并解决指令相互依赖性; 指令分配单元（IDU），包括地址生成互锁（AGI）和操作数提取逻辑，用于向至少一个加载存储单元和执行单元分发指令; 其中所述加载存储单元被配置为访问数据高速缓存并且将获取的数据返回到所述执行单元; 其中所述执行单元被配置为将数据写入通用寄存器组; 并且其中所述体系结构提供了对在写入通用寄存器组之前在执行单元中执行这种指令的地址生成的负载多重指令的结果的旁路支持。 还提供了一种方法和计算机系统。

公开(公告)号：US07971034B2

公开(公告)日：2011-06-28

申请号：US12051415

申请日：2008-03-19

申请人： David S. Hutton ,  Michael Billeci ,  Fadi Y. Busaba ,  Brian R. Prasky ,  John G. Rell, Jr. ,  Chung-Lung Kevin Shum ,  Charles F. Webb

发明人： David S. Hutton ,  Michael Billeci ,  Fadi Y. Busaba ,  Brian R. Prasky ,  John G. Rell, Jr. ,  Chung-Lung Kevin Shum ,  Charles F. Webb

IPC分类号： G06F9/00 ,  G06F9/44 ,  G06F9/30

CPC分类号： G06F9/30189 ,  G06F9/30076 ,  G06F9/342 ,  G06F9/3802 ,  G06F9/3824 ,  G06F9/3836 ,  G06F9/3861 ,  G06F9/3867

摘要： A method, system, and computer program product for reduced overhead address mode change management in a pipelined, recycling microprocessor are provided. The recycling microprocessor includes logic executing thereon. The microprocessor also includes an instruction fetch unit (IFU) supporting computation of address adds in selected address modes and reporting non-equal comparison of the computation to the logic. The microprocessor further includes a fixed point unit determining whether the mode has changed and reporting changes to the logic. Upon determining the comparison yields an equal result but the mode has changed, a recycle event is triggered to ensure subsequent ofetches are relaunched in the correct mode and that no execution writebacks occur from work performed in an incorrect mode. For comparisons yielding a non-equal result and a changed mode, the logic clears bits set in response to the determinations, and a serialization event is taken to reset a corresponding pipeline for operation in the correct mode.

摘要翻译： 提供了一种用于在流水线式回收微处理器中减少开销地址模式改变管理的方法，系统和计算机程序产品。 回收微处理器包括在其上执行的逻辑。 微处理器还包括一个指令提取单元（IFU），用于支持在所选择的地址模式中添加的地址的计算，并且将该计算的不相等的比较报告给逻辑。 微处理器还包括确定模式是否改变并且对逻辑进行报告改变的固定点单元。 在确定比较时，产生相等的结果，但是模式已经改变，触发一个循环事件，以确保以正确的模式重新启动后续的提取，并且在不正确的模式下执行的工作不会执行执行回写。 为了比较产生不相等的结果和改变的模式，逻辑清除响应于确定的位设置，并且采用串行化事件来复位相应的流水线以便以正确的模式进行操作。

公开(公告)号：US20090240929A1

公开(公告)日：2009-09-24

申请号：US12051415

申请日：2008-03-19

申请人： David S. Hutton ,  Michael Billeci ,  Fadi Y. Busaba ,  Brian R. Prasky ,  John G. Rell, JR. ,  Chung-Lung Kevin Shum ,  Charles F. Webb

发明人： David S. Hutton ,  Michael Billeci ,  Fadi Y. Busaba ,  Brian R. Prasky ,  John G. Rell, JR. ,  Chung-Lung Kevin Shum ,  Charles F. Webb

IPC分类号： G06F9/312

CPC分类号： G06F9/30189 ,  G06F9/30076 ,  G06F9/342 ,  G06F9/3802 ,  G06F9/3824 ,  G06F9/3836 ,  G06F9/3861 ,  G06F9/3867

摘要： A method, system, and computer program product for reduced overhead address mode change management in a pipelined, recycling microprocessor are provided. The recycling microprocessor includes logic executing thereon. The microprocessor also includes an instruction fetch unit (IFU) supporting computation of address adds in selected address modes and reporting non-equal comparison of the computation to the logic. The microprocessor further includes a fixed point unit determining whether the mode has changed and reporting changes to the logic. Upon determining the comparison yields an equal result but the mode has changed, a recycle event is triggered to ensure subsequent ofetches are relaunched in the correct mode and that no execution writebacks occur from work performed in an incorrect mode. For comparisons yielding a non-equal result and a changed mode, the logic clears bits set in response to the determinations, and a serialization event is taken to reset a corresponding pipeline for operation in the correct mode.

摘要翻译： 提供了一种用于在流水线式回收微处理器中减少开销地址模式改变管理的方法，系统和计算机程序产品。 回收微处理器包括在其上执行的逻辑。 微处理器还包括一个指令提取单元（IFU），用于支持在所选择的地址模式中添加的地址的计算，并且将该计算的不相等的比较报告给逻辑。 微处理器还包括确定模式是否改变并且对逻辑进行报告改变的固定点单元。 在确定比较时，产生相等的结果，但是模式已经改变，触发一个循环事件，以确保以正确的模式重新启动后续的提取，并且在不正确的模式下执行的工作不会执行执行回写。 为了比较产生不相等的结果和改变的模式，逻辑清除响应于确定的位设置，并且采用串行化事件来复位相应的流水线以便以正确的模式进行操作。

公开(公告)号：US07987343B2

公开(公告)日：2011-07-26

申请号：US12051527

申请日：2008-03-19

申请人： Khary J. Alexander ,  Fadi Y. Busaba ,  Vimal M. Kapadia ,  Chung-Lung Kevin Shum

发明人： Khary J. Alexander ,  Fadi Y. Busaba ,  Vimal M. Kapadia ,  Chung-Lung Kevin Shum

IPC分类号： G06F9/40 ,  G06F9/30

CPC分类号： G06F9/3867 ,  G06F9/30043 ,  G06F9/3826 ,  G06F9/3838 ,  G06F9/3857

摘要： A pipelined processor including an architecture for address generation interlocking, the processor including: an instruction grouping unit to detect a read-after-write dependency and to resolve instruction interdependency; an instruction dispatch unit (IDU) including address generation interlock (AGI) and operand fetching logic for dispatching an instruction to at least one of a load store unit and an execution unit; wherein the load store unit is configured with access to a data cache and to return fetched data to the execution unit; wherein the execution unit is configured to write data into a general purpose register bank; and wherein the architecture provides support for bypassing of results of a load multiple instruction for address generation while such instruction is executing in the execution unit before the general purpose register bank is written. A method and a computer system are also provided.

摘要翻译： 一种流水线处理器，包括用于地址生成互锁的架构，所述处理器包括：指令分组单元，用于检测写后依赖关系并解决指令相互依赖性; 指令分配单元（IDU），包括地址生成互锁（AGI）和操作数提取逻辑，用于向至少一个加载存储单元和执行单元分发指令; 其中所述加载存储单元被配置为访问数据高速缓存并且将获取的数据返回到所述执行单元; 其中所述执行单元被配置为将数据写入通用寄存器组; 并且其中所述体系结构提供了对在写入通用寄存器组之前在执行单元中执行这种指令的地址生成的负载多重指令的结果的旁路支持。 还提供了一种方法和计算机系统。