公开(公告)号：US5625836A

公开(公告)日：1997-04-29

申请号：US459374

申请日：1995-06-02

申请人： Thomas N. Barker ,  Clive A. Collins ,  Michael C. Dapp ,  James W. Dieffenderfer ,  Donald M. Lesmeister ,  Richard E. Nier ,  Eric E. Retter ,  Robert R. Richardson ,  Vincent J. Smoral

发明人： Thomas N. Barker ,  Clive A. Collins ,  Michael C. Dapp ,  James W. Dieffenderfer ,  Donald M. Lesmeister ,  Richard E. Nier ,  Eric E. Retter ,  Robert R. Richardson ,  Vincent J. Smoral

IPC分类号： G06F7/57 ,  G06F9/30 ,  G06F9/318 ,  G06F9/38 ,  G06F15/173 ,  G06F15/80 ,  G06F15/16

CPC分类号： G06F15/17337 ,  G06F15/17343 ,  G06F15/17368 ,  G06F15/17381 ,  G06F15/8007 ,  G06F15/803 ,  G06F7/483 ,  G06F9/3885 ,  G06F9/3887 ,  G06F9/3889

摘要： A parallel array processor for massively parallel applications is formed with low power CMOS with DRAM processing while incorporating processing elements on a single chip. Eight processors on a single chip have their own associated processing element, significant memory, and I/O and are interconnected with a hypercube based, but modified, topology. These nodes are then interconnected, either by a hypercube, modified hypercube, or ring, or ring within ring network topology. Conventional microprocessor MMPs consume pins and time going to memory. The new architecture merges processor and memory with multiple PMEs (eight 16 bit processors with 32K and I/O) in DRAM and has no memory access delays and uses all the pins for networking. The chip can be a single node of a fine-grained parallel processor. Each chip will have eight 16 bit processors, each processor providing 5 MIPs performance. I/O has three internal ports and one external port shared by the plural processors on the chip. Significant software flexibility is provided to enable quick implementation of existing programs written in common languages. It is a developable and expandable technology without need to develop new pinouts, new software, or new utilities as chip density increases and new hardware is provided for a chip function. The scalable chip PME has internal and external connections for broadcast and asynchronous SIMD, MIMD and SIMIMD (SIMD/MIMD) with dynamic switching of modes. The chip can be used in systems which employ 32, 64 or 128,000 processors, and can be used for lower, intermediate and higher ranges. Local and global memory functions can all be provided by the chips themselves, and the system can connect to and support other global memories and DASD. The chip can be used as a microprocessor accelerator, in personal computer applications, as a vision or avionics computer system, or as workstation or supercomputer. There is program compatibility for the fully scalable system.

公开(公告)号：US5617577A

公开(公告)日：1997-04-01

申请号：US400687

申请日：1995-03-08

申请人： Thomas N. Barker ,  Clive A. Collins ,  Michael C. Dapp ,  James W. Dieffenderfer ,  Donald G. Grice ,  Billy J. Knowles ,  Donald M. Lesmeister ,  Richard E. Nier ,  Eric E. Retter ,  David B. Rolfe ,  Vincent J. Smoral

发明人： Thomas N. Barker ,  Clive A. Collins ,  Michael C. Dapp ,  James W. Dieffenderfer ,  Donald G. Grice ,  Billy J. Knowles ,  Donald M. Lesmeister ,  Richard E. Nier ,  Eric E. Retter ,  David B. Rolfe ,  Vincent J. Smoral

IPC分类号： G06F7/57 ,  G06F9/30 ,  G06F9/318 ,  G06F9/38 ,  G06F15/173 ,  G06F15/80 ,  G06F13/00

CPC分类号： G06F7/483 ,  G06F15/17337 ,  G06F15/17343 ,  G06F15/17381 ,  G06F15/8007

摘要： A fast I/O for a multi-PME computer system provides a way to break into a network coupling to alternate network couplings. The system coupling is called a zipper.Our I/O zipper concept can be used to implement the concept that the port into a node could be driven by the port out of a node or by data coming from the system bus. Conversely, data being put out of a node would be available to both the input to another node and to the system bus. Outputting data to both the system bus and another node is not done simultaneously but in different cycles. The zipper passes data into and out of a network of interconnected nodes is used in a system of interconnecting nodes in a mesh, rings of wrapped tori. such that there is no edge to the network, the zipper mechanism logically breaks the the rings along a dimension orthogonal to the rings such that an edge to the network is established. The coupling dynamically toggles the network between a network without an edge and a network with an edge. Data passes into the network or out of the network through the edge when it is active, and the coupling permits dispersal of data entering the network or collection of data leaving the network such that the data rate through the edge matches both the sustained and peak data rates of the system external to the network.

摘要翻译： 多PME计算机系统的快速I / O提供了一种方法，可以将网络耦合到备用网络耦合中。 系统耦合称为拉链。 我们的I / O拉链概念可用于实现端口到节点中的端口可以由节点驱动的端口或来自系统总线的数据的概念。 相反，放出节点的数据对于另一个节点和系统总线的输入将是可用的。 将数据输出到系统总线和另一个节点都不是同时进行，而是在不同的周期内完成。 拉链将数据传入和传出互连节点的网络用于网状互连节点的系统，包裹圆环的环。 使得网络没有边缘，拉链机构沿着与环正交的尺寸逻辑地断开环，使得建立到网络的边缘。 耦合动态地在无边缘的网络和具有边缘的网络之间切换网络。 当数据有效时，数据通过边缘进入网络或网络，并且耦合允许分散进入网络的数据或离开网络的数据收集，使得通过边缘的数据速率与持续和峰值数据匹配 网络外部系统的速率。

公开(公告)号：US5588152A

公开(公告)日：1996-12-24

申请号：US519859

申请日：1995-08-25

申请人： Michael C. Dapp ,  Thomas N. Barker ,  James W. Dieffenderfer ,  Billy J. Knowles ,  Donald M. Lesmeister ,  Richard E. Nier ,  David B. Rolfe ,  Vincent J. Smoral

发明人： Michael C. Dapp ,  Thomas N. Barker ,  James W. Dieffenderfer ,  Billy J. Knowles ,  Donald M. Lesmeister ,  Richard E. Nier ,  David B. Rolfe ,  Vincent J. Smoral

IPC分类号： F02B75/02 ,  G06F7/57 ,  G06F9/30 ,  G06F9/318 ,  G06F9/38 ,  G06F15/173 ,  G06F15/80

CPC分类号： G06F9/3889 ,  G06F15/17337 ,  G06F15/17343 ,  G06F15/17368 ,  G06F15/17381 ,  G06F15/8007 ,  G06F15/8015 ,  G06F15/803 ,  G06F7/483 ,  G06F9/30 ,  G06F9/30036 ,  G06F9/30145 ,  G06F9/30167 ,  G06F9/3017 ,  G06F9/30181 ,  G06F9/30189 ,  G06F9/3802 ,  G06F9/3834 ,  G06F9/3836 ,  G06F9/3838 ,  G06F9/3851 ,  G06F9/3885 ,  G06F9/3887 ,  G06F9/3891 ,  F02B2075/027

摘要： A parallel array processor for massively parallel applications is formed with low power CMOS with DRAM processing while incorporating processing elements on a single chip. Eight processors on a single chip have their own associated processing element, significant memory, and I/O and are interconnected with a hypercube based, but modified, topology. These nodes are then interconnected, either by a hypercube, modified hypercube, or ring, or ring within ring network topology. Conventional microprocessor MMPs consume pins and time going to memory. The new architecture merges processor and memory with multiple PMEs (eight 16 bit processors with 32K and I/O) in DRAM and has no memory access delays and uses all the pins for networking. The chip can be a single node of a fine-grained parallel processor. Each chip will have eight 16 bit processors, each processor providing 5 MIPs performance. I/O has three internal ports and one external port shared by the plural processors on the chip. Significant software flexibility is provided to enable quick implementation of existing programs written in common languages. It is a developable and expandable technology without need to develop new pinouts, new software, or new utilities as chip density increases and new hardware is provided for a chip function. The scalable chip PME has internal and external connections for broadcast and asynchronous SIMD. MIMD and SIMIMD (SIMD/MIMD) with dynamic switching of modes. The chip can be used in systems which employ 32, 64 or 128,000 processors, and can be used for lower, intermediate and higher ranges. Local and global memory functions can all be provided by the chips themselves, and the system can connect to and support other global memories and DASD. The chip can be used as a microprocessor accelerator, in personal computer applications, as a vision or avionics computer system, or as workstation or supercomputer. There is program compatibility for the fully scalable system.

公开(公告)号：US5608448A

公开(公告)日：1997-03-04

申请号：US419474

申请日：1995-04-10

申请人： Vincent J. Smoral ,  Peter M. Kogge ,  Phillip J. Sementilli, Jr.

发明人： Vincent J. Smoral ,  Peter M. Kogge ,  Phillip J. Sementilli, Jr.

IPC分类号： H04L12/56 ,  H04N7/173 ,  H04N21/21 ,  H04N21/23 ,  H04Q11/04 ,  H04N7/10

CPC分类号： H04N21/21 ,  H04L49/106 ,  H04L49/1553 ,  H04L49/3081 ,  H04N21/23 ,  H04N7/17336 ,  H04Q11/0478 ,  H04L2012/561 ,  H04L2012/5642

摘要： Processing requirement at each computing element in a video server for a video on demand (VOD) system are reduced to only those needed for VOD, resulting in a less expensive processor with less memory and, hence, lower cost. A hybrid video server architecture combines the best features of massive parallel processor (MPP) and workstation designs into a cost effective high performance system. Since it is not necessary to run a parallel relational database program in order to accomplish VOD data distribution, a unique type of switch element that is well matched to the VOD server problem is employed. By matching this switch element technology to an appropriate data storage technique, a full featured, responsive VOD server is realized that can be affordably installed at regional cable distribution centers nationwide.

摘要翻译： 用于视频点播（VOD）系统的视频服务器中的每个计算元件的处理要求仅减少到VOD所需的处理要求，导致较便宜的处理器，具有较少的存储器，并因此降低成本。 混合视频服务器架构将大规模并行处理器（MPP）和工作站设计的最佳功能结合成一个具有成本效益的高性能系统。 由于不需要运行并行关系数据库程序来完成VOD数据分发，所以采用与VOD服务器问题很好匹配的独特类型的交换单元。 通过将这种开关元件技术与适当的数据存储技术相结合，实现了一个功能全面的响应式VOD服务器，可以经济地安装在全国的区域电缆分销中心。

公开(公告)号：US5590345A

公开(公告)日：1996-12-31

申请号：US887630

申请日：1992-05-22

申请人： Thomas N. Barker ,  Clive A. Collins ,  Michael C. Dapp ,  James W. Dieffenderfer ,  Donald G. Grice ,  Peter M. Kogge ,  David C. Kuchinski ,  Billy J. Knowles ,  Donald M. Lesmeister ,  Richard E. Miles ,  Richard E. Nier ,  Eric E. Retter ,  Robert R. Richardson ,  David B. Rolfe ,  Nicholas J. Schoonover ,  Vincent J. Smoral ,  James R. Stupp ,  Paul A. Wilkinson

发明人： Thomas N. Barker ,  Clive A. Collins ,  Michael C. Dapp ,  James W. Dieffenderfer ,  Donald G. Grice ,  Peter M. Kogge ,  David C. Kuchinski ,  Billy J. Knowles ,  Donald M. Lesmeister ,  Richard E. Miles ,  Richard E. Nier ,  Eric E. Retter ,  Robert R. Richardson ,  David B. Rolfe ,  Nicholas J. Schoonover ,  Vincent J. Smoral ,  James R. Stupp ,  Paul A. Wilkinson

IPC分类号： F02B75/02 ,  G06F7/57 ,  G06F9/30 ,  G06F9/318 ,  G06F9/38 ,  G06F15/173 ,  G06F15/80 ,  G06F13/00

CPC分类号： G06F7/483 ,  G06F15/17337 ,  G06F15/17343 ,  G06F15/17368 ,  G06F15/17381 ,  G06F15/8007 ,  G06F15/8015 ,  G06F15/803 ,  G06F15/8092 ,  G06F9/30036 ,  G06F9/30145 ,  G06F9/30167 ,  G06F9/30189 ,  G06F9/3834 ,  G06F9/3851 ,  G06F9/3885 ,  G06F9/3887 ,  G06F9/3889 ,  G06F9/3891 ,  F02B2075/027

摘要： A computer system having a plurality of processors and memory including a plurality of scalable nodes having multiple like processor memory elements. Each of the processor memory elements has a plurality of communication paths for communication within a node to other like processor memory elements within the node. Each of the processor memory elements also has a communication path for communication external to the node to another like scalable node of the computer system.

摘要翻译： 一种具有多个处理器和存储器的计算机系统，所述存储器包括具有多个相似处理器存储器元件的多个可伸缩节点。 每个处理器存储器元件具有用于在节点内与节点内的其它类似处理器存储器元件通信的多个通信路径。 每个处理器存储器元件还具有用于将节点外部通信到另一个类似计算机系统的可伸缩节点的通信路径。