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公开(公告)号：US5111192A
公开(公告)日：1992-05-05
申请号：US453738
申请日：1989-12-20
申请人： Vinod K. Kadakia
发明人： Vinod K. Kadakia
IPC分类号： G06T3/60
CPC分类号： G06T3/602
摘要： An algorithm for rotating an image 90 degrees starts with an array or r rows and c columns of pixels. Each column of the pixel array is partitioned into words of w pixels each, and the rows, the columns, the words in each column, and the pixels in each word of the pixel array are all numbered starting at zero. Let v= r/w , where r/w is the smallest integer greater than or equal to r/w. Similarly, let h- c/w . The algorithm stores words of the original pixel array into a linear word organized memory as follows: it circular right-shifts each word i of column j by (j)mod w pixel positions and then writes in parallel this modified word into word address vj+i of the memory. The algorithm fetches words of the stored pixel array from this memory rotating this pixel array 90 degrees as follows: it reads a whole word in parallel such that each pixel p of this word comes from pixel p of word address wvi+v((p+j+1)mod w)+ wv-j-1/w) and then circular right-shifts this word by (j+1)mod w pixel positions, thereby delivering word i of column j of a 90 degree rotated version of the original pixel array.
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2.发明授权Circuit for fast page mode addressing of a RAM with multiplexed row and column address lines 失效具有复用行和列地址线的RAM快速寻址模式的电路
公开(公告)号：US5361339A
公开(公告)日：1994-11-01
申请号：US878192
申请日：1992-05-04
IPC分类号： G06F12/00 , G06T1/60 , G06T3/60 , G09G5/36 , G11C7/10 , G11C11/401 , H04N1/387 , G09G5/38 , G11C8/00
CPC分类号： G06T3/606 , G11C7/1021
摘要： A circuit for addressing a random access memory (RAM) and for rotating an image by reading it into and then out from a page buffer, where all transfers, whether by column or row, are performed substantially in a fast page mode in which the same row address is maintained from one access to the next. The column address lines of RAM devices are connected to the 5 or 6 least significant bits of the vertical and horizontal address counters of the image, and the row address lines are connected to the remaining most significant bits of the vertical and horizontal counters of the image. Therefore, whether the system is accessing the image data in the vertical or horizontal direction, there will be at least 31 fast page mode accesses for every one slow access, and the average speed of transfers in either direction will approximate the fast page mode speed.
摘要翻译： 用于寻址随机存取存储器（RAM）并通过将图像读入页面缓冲器而转移到图像缓冲器中的电路，其中所有传送（无论是通过列还是行）都基本上以相同的快速页面模式执行 行地址从一个访问维护到下一个。 RAM设备的列地址线连接到图像的垂直和水平地址计数器的5或6个最低有效位，并且行地址线连接到图像的垂直和水平计数器的剩余最高有效位 。 因此，无论系统是在垂直方向还是水平方向上访问图像数据，对于每一个慢速访问将存在至少31次快速页面模式访问，并且任一方向的平均传输速度将接近快速页面模式速度。
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公开(公告)号：US4425582A
公开(公告)日：1984-01-10
申请号：US293815
申请日：1981-08-17
申请人： Vinod K. Kadakia , Glen D. Jones
发明人： Vinod K. Kadakia , Glen D. Jones
IPC分类号： G06T9/00 , H04N1/41 , H04N1/417 , H03K13/243
CPC分类号： G06T9/004 , G06T9/005 , H04N1/4105 , H04N1/417
摘要： A predictor bit pattern comprising selected bits of the current and previous raster scan lines and a method of predicting a plurality of bits per clock are disposed. Generally, a predictor is used prior to the encoding of data to increase the compression. The current bit in a bit stream is compared to the predicted value and a one is output when the two values are not equal. An efficient predictor will reduce the number of ones in a bit stream, which increases the zero run lengths and increases the efficiency of a run length encoding system. The described bit pattern contains bits close to the current bit to efficiently predict text data, bits distant from the current bit to efficiently predict halftone data, and ignores a plurality of intermediate bits to reduce hardware costs. A two step process is also described to allow a plurality of bits to be predicted in parallel. A circuit for performing this process comprises a buffer for storing the previous and current line data, two registers for holding the previous and current line prediction data patterns and two PROMs for performing the two step prediction.
摘要翻译： 布置包括当前和之前的光栅扫描线的选定位的预测器位模式以及每个时钟预测多个位的方法。 通常，在数据编码之前使用预测器来增加压缩。 将比特流中的当前比特与预测值进行比较，并且当两个值不相等时输出一个。 有效的预测器将减少位流中的数量，这增加了零运行长度，并提高了运行长度编码系统的效率。 所描述的位模式包含靠近当前位的位以有效地预测文本数据，远离当前位的位以有效地预测半色调数据，并忽略多个中间位以降低硬件成本。 还描述了两步处理以允许并行预测多个位。 用于执行该处理的电路包括用于存储先前和当前行数据的缓冲器，用于保持先前和当前行预测数据模式的两个寄存器和用于执行两步预测的两个PROM。
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公开(公告)号：US5365601A
公开(公告)日：1994-11-15
申请号：US811865
申请日：1991-12-23
CPC分类号： G06T3/60
摘要： A circuit for rapidly rotating a digital image through 90 or 270 degrees utilizing memory implemented from ordinary 4-bit wide memory devices. This pipelined circuit transfers the image through a page buffer and a band buffer in a series of memory accessing, shining and reordering steps which converts all vertical lines to horizontal lines and all horizontal lines to vertical lines without requiring the use of a parallel to serial conversion.
摘要翻译： 一种用于通过使用从普通4位宽存储器件实现的存储器使数字图像快速旋转90或270度的电路。 这种流水线电路通过页缓冲器和带缓冲器将图像传送到一系列存储器访问，闪烁和重排序步骤，其将所有垂直线转换成水平线，将所有水平线转换成垂直线，而不需要使用并行到串行转换 。
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公开(公告)号：US4327379A
公开(公告)日：1982-04-27
申请号：US139501
申请日：1980-04-11
摘要： A circuit to encode image data. The circuit receives image data in four bit nibbles which are either all-zero nibbles or terminating nibbles containing at least one non-zero bit. The circuit output is a series of code words, each a multiple of four bits and up to twenty-four bits long, packed into eight bit output words. Each code word contains a first part containing a run length specifying the number of received all-zero nibbles and a second part specifying the bit pattern of the terminating nibble. The circuit uses PROMs for the look-up and control elements and a pipeline of registers to allow high speed operation.
摘要翻译： 用于对图像数据进行编码的电路。 该电路接收四位半字节中的图像数据，它们是包含至少一个非零位的全零半字节或终止半字节。 电路输出是一系列代码字，每一个是四位数，最多二十四位，多达八位输出字。 每个代码字包含包含指定接收的全零半字节的数量的游程长度的第一部分和指定终止半字节的位模式的第二部分。 该电路使用PROM来查找和控制元件以及一个寄存器流水线，以允许高速运行。
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