Adapter for raster output scanning printer
    1.
    发明授权
    Adapter for raster output scanning printer 失效
    光栅输出扫描打印机适配器

    公开(公告)号:US4279002A

    公开(公告)日:1981-07-14

    申请号:US899137

    申请日:1978-04-24

    申请人: Ronald E. Rider

    发明人: Ronald E. Rider

    CPC分类号: G06K15/128

    摘要: An adapter is provided as an interface between a raster output scanning printer and an electronic image processor which formats digital information for use by the printer in creating printed images. The adapter accepts digital pulses through a structured array of communication lines from the electronic image processor. Each line is dedicated to the provision of certain video or control information which may be utilized by any one of a number of different raster output scanning printers. The electronic image processor is indifferent to the identity of the type of printer to which information is provided as the adapter serves to manipulate the data provided by the electronic image processor in a manner suitable to control the particular printer employed. The adapter is sensitive to the scanning cycles of the printer and accommodates deviations in scan time to increase or decrease the rate of provision of video information in accordance with fluctuations in printer motor speed. A phase lock loop with the printer motor is provided for this purpose. The adapter also multiplexes status information of operating conditions generated internally and from the printer, and serially sends this status information to the electronic image processor.

    摘要翻译: 提供适配器作为光栅输出扫描打印机和电子图像处理器之间的接口,其格式化数字信息以供打印机在创建打印图像时使用。 适配器通过来自电子图像处理器的通信线路的结构化阵列接受数字脉冲。 每条线专用于提供可由多个不同的光栅输出扫描打印机中的任何一个使用的某些视频或控制信息。 电子图像处理器对于适配器用于以适合于控制所使用的特定打印机的方式来操纵由电子图像处理器提供的数据的打印机类型的身份无动于衷。 适配器对打印机的扫描周期敏感,并适应扫描时间的偏差,以根据打印机电机速度的波动增加或减少视频信息的提供速率。 为此,提供了带有打印机电机的锁相环。 适配器还多路复用内部生成的操作条件和打印机的状态信息,并将该状态信息串行发送到电子图像处理器。

    Process for sequentially reading a page from an image memory in either
of two directions
    4.
    发明授权
    Process for sequentially reading a page from an image memory in either of two directions 失效
    用于在两个方向中的任一方向上从图像存储器顺序读取页面的处理

    公开(公告)号:US5561777A

    公开(公告)日:1996-10-01

    申请号:US114552

    申请日:1993-08-30

    CPC分类号: G11C8/00 G11C7/103 G11C8/12

    摘要: A process of loading an image in the form of a bit map into a memory which can transfer data words in burst mode in either row or column direction. First, the memory is divided into two sections with odd words stored in one section, even in the other, which allows ping pong buffers to be reading one word from memory while the next is being accessed. Also, the page height is set to be an odd number of words. Therefore, when the entire page is read in or out, successive words in either the row or column direction will always be alternately odd and even. If a partial image is read into the memory, this odd and even relationship will also hold. If an image with an even number of rows is read in, in order to preserve the sequential odd-even sequence, in every other column of the original data successive words are swapped so that the word order becomes 1, 0, 3, 2, etc. Then the addresses are also generated in staggered order, so that the words go into the correct location in memory. In this way, the word order of loading and reading of data is always successively odd and even regardless of the size of the image.

    摘要翻译: 以位图的形式将图像加载到存储器中的过程,该存储器可以在行或列方向上以突发模式传送数据字。 首先,存储器被分成两部分,其中一个部分存储有奇数字,即使在另一部分中,也允许乒乓缓冲器在下一个被访问时从存储器读取一个字。 此外,页面高度被设置为奇数个字。 因此,当整个页面被读取或读出时,行或列方向上的连续字将总是交替地奇偶校验。 如果将部分图像读入存储器,则这种奇数和偶数关系也将成立。 如果读入具有偶数行的图像,为了保留顺序奇偶序列,在原始数据的每隔一列中连续字被交换,使得字顺序变为1,0,3,2, 然后地址也以交错的顺序生成,使得这些词进入存储器中的正确位置。 以这种方式,加载和读取数据的单词顺序总是连续地奇数,甚至不管图像的大小。

    Hardware implementation of 4-pixel code encoder
    5.
    发明授权
    Hardware implementation of 4-pixel code encoder 失效
    硬件实现4像素代码编码器

    公开(公告)号:US4327379A

    公开(公告)日:1982-04-27

    申请号:US139501

    申请日:1980-04-11

    CPC分类号: G06T9/005 H03M7/46 H04N1/415

    摘要: A circuit to encode image data. The circuit receives image data in four bit nibbles which are either all-zero nibbles or terminating nibbles containing at least one non-zero bit. The circuit output is a series of code words, each a multiple of four bits and up to twenty-four bits long, packed into eight bit output words. Each code word contains a first part containing a run length specifying the number of received all-zero nibbles and a second part specifying the bit pattern of the terminating nibble. The circuit uses PROMs for the look-up and control elements and a pipeline of registers to allow high speed operation.

    摘要翻译: 用于对图像数据进行编码的电路。 该电路接收四位半字节中的图像数据,它们是包含至少一个非零位的全零半字节或终止半字节。 电路输出是一系列代码字,每一个是四位数,最多二十四位,多达八位输出字。 每个代码字包含包含指定接收的全零半字节的数量的游程长度的第一部分和指定终止半字节的位模式的第二部分。 该电路使用PROM来查找和控制元件以及一个寄存器流水线,以允许高速运行。

    Parallel run-length decoder
    6.
    发明授权
    Parallel run-length decoder 失效
    并行游程解码器

    公开(公告)号:US4152697A

    公开(公告)日:1979-05-01

    申请号:US713544

    申请日:1976-08-11

    摘要: System and method for parallel decoding of character data in run length format to produce data in dot matrix form for presentation to a display device. The data for successive runs is stored in registers and processed in parallel to provide address data for memory devices programmed to deliver predetermined output data patterns in response to the address data.

    摘要翻译: 用于以游程长度格式并行解码字符数据的系统和方法以产生用于呈现给显示设备的点阵形式的数据。 用于连续运行的数据被存储在寄存器中并且被处理以提供编程为响应于地址数据传送预定输出数据模式的存储器件的地址数据。

    Set of run-length codewords containing printing hints
    7.
    发明授权
    Set of run-length codewords containing printing hints 有权
    包含打印提示的游程长度码字集

    公开(公告)号:US06307977B1

    公开(公告)日:2001-10-23

    申请号:US09193185

    申请日:1998-11-17

    IPC分类号: G06K936

    CPC分类号: H04N19/93

    摘要: A run length codeword system which has a set of codewords, each codeword being one byte. The first codeword of a run is divided into a 4-bit code part and 4 bits of printing hints. The code part specifies the source of the data, and the format of the remaining bytes in the run. The remaining one or two codewords specify the number of remaining data bytes in the run, or color values.

    摘要翻译: 具有一组码字的游程长度码字系统,每个码字是一个字节。 运行的第一个代码字被分为4位代码部分和4位打印提示。 代码部分指定数据的源,以及运行中剩余字节的格式。 剩余的一个或两个码字指定运行中剩余的数据字节数,或颜色值。

    High resolution character generator
    8.
    发明授权
    High resolution character generator 失效
    高分辨率字符发生器

    公开(公告)号:US4079458A

    公开(公告)日:1978-03-14

    申请号:US713545

    申请日:1976-08-11

    CPC分类号: G09G5/42 G06K15/128 G09G5/24

    摘要: High resolution character generator for producing rows of characters to be scanned on a display medium. Input data defining characters to be printed in ordered rows of text is sorted to provide specifications for the characters which being on each successive scan line. These specifications are stored initially in an input buffer, and specifications for characters which have been partially printed in a previous scan line are stored in an active character buffer. For each scan line, the character specifications are read first from the active character buffer and then from the input buffer until an end of line specifier is reached. For each character specification received, a font memory containing data defining the characters is cycled. The data from the font memory is decoded and presented to the display medium on a line by line basis.

    摘要翻译: 用于产生要在显示介质上扫描的字符行的高分辨率字符发生器。 定义要按有序行文字打印的字符的输入数据进行排序,以便为每个连续扫描行上的字符提供规格。 这些规范最初存储在输入缓冲器中,并且已经部分地打印在先前扫描行中的字符的规格被存储在活动字符缓冲器中。 对于每条扫描线,首先从活动字符缓冲区读取字符规格,然后从输入缓冲区读取字符规格,直到到达行尾说明符。 对于接收到的每个字符规范,循环包含定义字符的数据的字体存储器。 来自字体存储器的数据被解码并逐行呈现给显示介质。

    Virtual memory cache for use in multi-processing systems
    9.
    发明授权
    Virtual memory cache for use in multi-processing systems 失效
    用于多处理系统的虚拟内存缓存

    公开(公告)号:US4843542A

    公开(公告)日:1989-06-27

    申请号:US930172

    申请日:1986-11-12

    IPC分类号: G06F12/08

    CPC分类号: G06F12/0833

    摘要: A system for maintaining data consistency among distributed processors, each having its associated cache memory. A processor addresses data in its cache by specifying the virtual address. The cache will search its cells for the data associatively. Each cell has a virtual address, a real address, flags and a plurality of associated data words. If there is no hit on the virtual address supplied by the processor, a map processor supplies the equivalent real address which the cache uses to access the data from another cache if one has it, or else from real memory. When a processor writes into a data word in the cache, the cache will update all other caches that share the data before allowing the write to the local cache.

    摘要翻译: 一种用于维护分布式处理器之间的数据一致性的系统,每个都具有其关联的高速缓存。 处理器通过指定虚拟地址来对其缓存中的数据进行寻址。 高速缓存将相关地搜索其单元格的数据。 每个单元具有虚拟地址,真实地址,标志和多个相关联的数据字。 如果处理器提供的虚拟地址没有命中,则映射处理器提供高速缓存用于从另一高速缓存访​​问数据的等效实地址(如果有的话),或者从实际存储器提供。 当处理器写入缓存中的数据字时,高速缓存将在允许写入本地缓存之前更新共享数据的所有其他高速缓存。

    Hybrid bit clock servo
    10.
    发明授权
    Hybrid bit clock servo 失效
    混合位时钟伺服

    公开(公告)号:US4320420A

    公开(公告)日:1982-03-16

    申请号:US165813

    申请日:1980-07-03

    申请人: Ronald E. Rider

    发明人: Ronald E. Rider

    摘要: A circuit for controlling the clock rate separately for each facet of a polygon used in a laser driven raster output scanner. The clock rate for facet #0 is servoed using a first order integrator (11) driven by a digital correction circuit which compares the actual number of pulses against the required number, and produces therefrom an analog correction pulse width which is applied to the integrator (11). A second order integrator (19) is used to compensate for leakage of charge from the parallel capacitor of the first order integrator (11), to improve performance. The remaining facets are then corrected for by assigning to each an individual correction voltage. This correction voltage is generated by counting clock pulses for each additional facet and using these pulse totals to generate individual analog correction voltages which are added to, or subtracted from the facet #0 voltage in an adder (18) which combines the facet #0 correction voltage with each individual voltage in sequence. The result is a relatively simple and inexpensive circuit that compensates for facet signature errors, as well as errors produced by drive motor hunting.

    摘要翻译: 用于在激光驱动的光栅输出扫描器中使用的多边形的每一个面分别控制时钟频率的电路。 使用由数字校正电路驱动的第一阶积分器(11)对面#0的时钟速率进行伺服,该数字校正电路将实际脉冲数与所需数量进行比较,并由此产生施加到积分器的模拟校正脉冲宽度 11)。 二阶积分器(19)用于补偿来自一阶积分器(11)的并联电容器的电荷泄漏,以提高性能。 然后通过分配每个单独的校正电压来校正剩余的面。 该校正电压通过对每个附加小面进行计数时钟脉冲并使用这些脉冲总数来产生单独的模拟校正电压来产生,所述各个模拟校正电压被加到加法器(18)中的或从小面#0电压中减去,该加法器组合了小面#0校正 每个电压按顺序进行。 结果是相对简单和廉价的电路,补偿了小平面签名错误,以及由驱动马达打猎产生的错误。