公开(公告)号：US20110173360A1

公开(公告)日：2011-07-14

申请号：US12859424

申请日：2010-08-19

Applicant: Steven S. Thomson ,  Ali Iranli ,  Michael J. Drop ,  Vinodh R. Cuppu ,  Christopher Kong Yee Chun ,  Tao Xue ,  Haw-Jing Lo ,  Moinul H. Kahn

Inventor： Steven S. Thomson ,  Ali Iranli ,  Michael J. Drop ,  Vinodh R. Cuppu ,  Christopher Kong Yee Chun ,  Tao Xue ,  Haw-Jing Lo ,  Moinul H. Kahn

IPC: G06F9/00 ,  G06F13/24

CPC classification number: G06F1/3203 ,  G06F1/324 ,  G06F1/3296 ,  Y02D10/126 ,  Y02D10/172

Abstract: A method of monitoring one or more central processing units in real time is disclosed. The method may include monitoring state data associated with the one or more CPUs in real-time, filtering the state data, and at least partially based on filtered state data, selectively altering one or more system settings.

Abstract translation: 公开了实时监控一个或多个中央处理单元的方法。 该方法可以包括：实时地监视与一个或多个CPU相关联的状态数据，过滤状态数据，并且至少部分地基于经过滤的状态数据，选择性地改变一个或多个系统设置。

公开(公告)号：US08352759B2

公开(公告)日：2013-01-08

申请号：US12859424

申请日：2010-08-19

Applicant: Steven S. Thomson ,  Ali Iranli ,  Michael J. Drop ,  Vinodh R. Cuppu ,  Christopher Kong Yee Chun ,  Tao Xue ,  Haw-Jing Lo ,  Moinul H. Kahn

Inventor： Steven S. Thomson ,  Ali Iranli ,  Michael J. Drop ,  Vinodh R. Cuppu ,  Christopher Kong Yee Chun ,  Tao Xue ,  Haw-Jing Lo ,  Moinul H. Kahn

IPC: G06F1/00

CPC classification number: G06F1/3203 ,  G06F1/324 ,  G06F1/3296 ,  Y02D10/126 ,  Y02D10/172

Abstract: A method of monitoring one or more central processing units in real time is disclosed. The method may include monitoring state data associated with the one or more CPUs in real-time, filtering the state data, and at least partially based on filtered state data, selectively altering one or more system settings.

Abstract translation: 公开了实时监控一个或多个中央处理单元的方法。 该方法可以包括：实时地监视与一个或多个CPU相关联的状态数据，过滤状态数据，并且至少部分地基于经过滤的状态数据，选择性地改变一个或多个系统设置。

公开(公告)号：US06948051B2

公开(公告)日：2005-09-20

申请号：US09855241

申请日：2001-05-15

Applicant: Jude A. Rivers ,  Jaime H. Moreno ,  Vinodh R. Cuppu

Inventor： Jude A. Rivers ,  Jaime H. Moreno ,  Vinodh R. Cuppu

IPC: G06F9/30 ,  G06F9/302 ,  G06F9/38 ,  G06F9/318

CPC classification number: G06F9/3891 ,  G06F9/30014 ,  G06F9/30036 ,  G06F9/30112 ,  G06F9/3012 ,  G06F9/3016 ,  G06F9/30192 ,  G06F9/3887

Abstract: A method and apparatus for reducing logic activity in a microprocessor which examines every instruction before it is executed and determines in advance the minimum appropriate datapath width (in byte or half-word quantities) necessary to accurately execute the operation. Achieving this requires two major enhancements to a traditional microprocessor pipeline. First, extra logic (potentially an extra pipeline stage for determining an operation's effective bit width—the WD width detection logic) is introduced between the Decode and Execution stages. Second, the traditional Execution stage architecture (including a register file RF and the arithmetic logical unit ALU), instead of being organized as one continuous 32-bit unit, is organized as a collection of multiple slices, where a slice can be of an 8-bit (a byte) or a 16-bit (double byte) granularity. Each slice in this case can operate independently of each other slice, and includes portion of the register file, functional unit and cache memory. Concatenating a multiple number of these slices together creates a required full width processor.

Abstract translation: 一种用于减少微处理器中的逻辑活动的方法和装置，其在执行之前检查每个指令，并且预先确定准确执行该操作所需的最小适当的数据路径宽度（以字节或半字数量）。 实现这一点需要对传统微处理器管道进行两个主要的改进。 首先，在解码和执行阶段之间引入额外的逻辑（潜在的用于确定操作的有效位宽度的额外流水线级 - WD宽度检测逻辑）。 第二，传统的执行阶段架构（包括寄存器文件RF和算术逻辑单元ALU）而不是组织为一个连续的32位单元，被组织为多个片段的集合，其中片可以是8 位（一个字节）或一个16位（双字节）粒度。 在这种情况下，每个切片可独立于每个切片进行操作，并且包括寄存器文件，功能单元和高速缓冲存储器的部分。 将多个这些切片连接在一起创建所需的全宽处理器。