公开(公告)号：US08407647B2

公开(公告)日：2013-03-26

申请号：US12970888

申请日：2010-12-16

申请人： Fong-Yuan Chang ,  Sheng-Hsiung Chen ,  Tung-Chieh Chen ,  Ren-Song Tsay ,  Wai-Kei Mak

发明人： Fong-Yuan Chang ,  Sheng-Hsiung Chen ,  Tung-Chieh Chen ,  Ren-Song Tsay ,  Wai-Kei Mak

IPC分类号： G06F17/50

CPC分类号： G06F17/5077 ,  G06F17/5068 ,  G06F17/5072 ,  G06F17/5081

摘要： A method for designing and making an integrated circuit is described. That method utilizes statistical models of wire segments to accurately estimate the expected length of minimum-length, orthogonal wire segments within a block. From these estimates, the method accurately estimates an ratio between the horizontal and vertical routing resources required, termed the “H/V Demand Ratio.” From the H/V Demand Ratio, an accurate estimate of the height and width of the block may be determined. Thereafter, placement and routing may be performed quickly and accurately, thereby allowing the block to be designed and manufactured quickly and cost effectively. A method for designing an integrated circuit with efficient metal-1 resource utilization is also described.

摘要翻译： 描述了一种用于设计和制造集成电路的方法。 该方法使用线段的统计模型来精确估计块内最小长度正交线段的预期长度。 从这些估计，该方法准确地估计所需的水平和垂直路由资源之间的比例，称为H / V需求比率。 根据H / V需求比，可以确定块的高度和宽度的准确估计。 此后，可以快速且准确地执行放置和布线，从而允许块被快速且成本有效地设计和制造。 还描述了一种设计具有有效的金属-1资源利用的集成电路的方法。

公开(公告)号：US20110154282A1

公开(公告)日：2011-06-23

申请号：US12970888

申请日：2010-12-16

申请人： Fong-Yuan CHANG ,  Sheng-Hsiung Chen ,  Tung-Chieh Chen ,  Ren-Song Tsay ,  Wai-Kei Mak

发明人： Fong-Yuan CHANG ,  Sheng-Hsiung Chen ,  Tung-Chieh Chen ,  Ren-Song Tsay ,  Wai-Kei Mak

IPC分类号： G06F17/50

CPC分类号： G06F17/5077 ,  G06F17/5068 ,  G06F17/5072 ,  G06F17/5081

摘要： A method for designing and making an integrated circuit is described. That method utilizes statistical models of wire segments to accurately estimate the expected length of minimum-length, orthogonal wire segments within a block. From these estimates, the method accurately estimates an ratio between the horizontal and vertical routing resources required, termed the “H/V Demand Ratio.” From the H/V Demand Ratio, an accurate estimate of the height and width of the block may be determined. Thereafter, placement and routing may be performed quickly and accurately, thereby allowing the block to be designed and manufactured quickly and cost effectively. A method for designing an integrated circuit with efficient metal-1 resource utilization is also described.

摘要翻译： 描述了一种用于设计和制造集成电路的方法。 该方法使用线段的统计模型来精确估计块内最小长度正交线段的预期长度。 根据这些估计，该方法精确地估计所需的水平和垂直路由资源之间的比例，称为“H / V需求比”。从H / V需求比率来看，块的高度和宽度的准确估计可以是 决心。 此后，可以快速且准确地执行放置和布线，从而允许块被快速且成本有效地设计和制造。 还描述了一种设计具有有效的金属-1资源利用的集成电路的方法。

公开(公告)号：US20110107278A1

公开(公告)日：2011-05-05

申请号：US12913674

申请日：2010-10-27

申请人： Fong-Yuan Chang ,  Wai-Kei Mak ,  Ren-Song Tsay

发明人： Fong-Yuan Chang ,  Wai-Kei Mak ,  Ren-Song Tsay

IPC分类号： G06F17/50

CPC分类号： G06F17/5077 ,  G06F2217/12 ,  Y02P90/265

摘要： A method and apparatus for manufacturing an integrated circuit (IC), the method including, generating, by a graphical construction unit, a first graph corresponding to a first net of the IC, the first graph representing a pin of the first net as a vertex, and a connection between two pins of the first net as an edge, the first graph further corresponding to a first IC layout; identifying a first and a second pair of unconnected vertices in the first graph for inserting a first and a second redundant edge, respectively, the first redundant edge and the second redundant edge forming a first connected loop and a second connected loop, respectively, each loop further including at least two edges of the first graph; calculating a tolerance ratio for the first redundant edge and the second redundant edge; sorting the first and second redundant edge based on their tolerance ratio; calculating a yield rate change of the first IC layout associated with inserting one of the first or second redundant edge with a highest tolerance ratio, and updating the first IC layout to include the redundant edge with the highest tolerance ratio if the yield rate change is greater than zero; and calculating the yield rate change of the first IC layout associated with inserting the first or second redundant edge having a second highest tolerance ratio, and updating the first IC layout to include the redundant edge with the second highest tolerance ratio if the yield rate change is greater than zero.

摘要翻译： 一种用于制造集成电路（IC）的方法和装置，所述方法包括：通过图形构造单元生成与所述IC的第一网络对应的第一图形，所述第一图形表示所述第一网络的针脚作为顶点 以及第一网的两个引脚之间的连接作为边缘，第一图形还对应于第一IC布局; 识别第一图中的第一和第二对未连接顶点，分别插入第一和第二冗余边缘，第一冗余边缘和第二冗余边缘分别形成第一连接环路和第二连接环路，每个环路 还包括所述第一图形的至少两个边缘; 计算第一冗余边缘和第二冗余边缘的容差比; 根据其容差比对第一和第二冗余边进行排序; 计算与插入具有最高容差比的第一或第二冗余边缘之一相关联的第一IC布局的产出率变化，以及如果产出率变化较大，则更新第一IC布局以包括具有最高容差比的冗余边缘 比零; 以及计算与插入具有第二高容差比的第一或第二冗余边缘相关联的第一IC布局的产出率变化，并且如果产出率变化为更新，则将第一IC布局更新为包括具有第二高容差比的冗余边缘 大于零。

公开(公告)号：US20090228844A1

公开(公告)日：2009-09-10

申请号：US12042978

申请日：2008-03-05

申请人： Wai Kei Mak ,  Wei Chung Chao

发明人： Wai Kei Mak ,  Wei Chung Chao

IPC分类号： G06F17/50

CPC分类号： G06F17/505 ,  G06F2217/62 ,  G06F2217/78

摘要： A method for reducing power consumption for an integrated circuit comprises the steps of (1) providing (i) a clock tree wherein the clock tree comprises a clock source, a plurality of clock sinks, and a plurality of internal nodes, (ii) the physical locations of the clock source, the clock sinks, and physical location of a gating-signal control logic circuit, (iii) the activity information of the sinks; (2) recursively determining a merging segment set containing merging segments for each internal node and computing switched capacitance of a subtree rooted at each internal node in a bottom up manner, wherein the merging segments have the same signal delay for the clock sinks in a subtree rooted at each internal node; and (3) recursively determining a location for each internal node selected from the merging segment set in a top down manner on a basis that the switched capacitance of a subtree rooted at each internal node is minimum.

摘要翻译： 一种用于降低集成电路的功耗的方法包括以下步骤：（1）提供（i）时钟树，其中时钟树包括时钟源，多个时钟汇和多个内部节点，（ii） 时钟源的物理位置，时钟信宿和门控信号控制逻辑电路的物理位置，（iii）汇点的活动信息; （2）递归地确定包含每个内部节点的合并段的合并段集合，并且以自下而上的方式计算以每个内部节点为根的子树的切换电容，其中合并段具有与子树中的时钟信宿相同的信号延迟 植根于每个内部节点; 并且（3）基于以每个内部节点为根的子树的切换电容为基础，以自顶向下的方式递归地确定从合并段选择的每个内部节点的位置。

公开(公告)号：US08336001B2

公开(公告)日：2012-12-18

申请号：US12913674

申请日：2010-10-27

申请人： Fong-Yuan Chang ,  Wai-Kei Mak ,  Ren-Song Tsay

发明人： Fong-Yuan Chang ,  Wai-Kei Mak ,  Ren-Song Tsay

IPC分类号： G06F17/50

CPC分类号： G06F17/5077 ,  G06F2217/12 ,  Y02P90/265

摘要： A method and apparatus for manufacturing an integrated circuit (IC), the method including, generating, by a graphical construction unit, a first graph corresponding to a first net of the IC, the first graph representing a pin of the first net as a vertex, and a connection between two pins of the first net as an edge, the first graph further corresponding to a first IC layout; identifying a first and a second pair of unconnected vertices in the first graph for inserting a first and a second redundant edge, respectively, the first redundant edge and the second redundant edge forming a first connected loop and a second connected loop, respectively, each loop further including at least two edges of the first graph; calculating a tolerance ratio for the first redundant edge and the second redundant edge; sorting the first and second redundant edge based on their tolerance ratio; calculating a yield rate change of the first IC layout associated with inserting one of the first or second redundant edge with a highest tolerance ratio, and updating the first IC layout to include the redundant edge with the highest tolerance ratio if the yield rate change is greater than zero; and calculating the yield rate change of the first IC layout associated with inserting the first or second redundant edge having a second highest tolerance ratio, and updating the first IC layout to include the redundant edge with the second highest tolerance ratio if the yield rate change is greater than zero.

摘要翻译： 一种用于制造集成电路（IC）的方法和装置，所述方法包括：通过图形构造单元生成与所述IC的第一网络对应的第一图形，所述第一图形表示所述第一网络的针脚作为顶点 以及第一网的两个引脚之间的连接作为边缘，第一图形还对应于第一IC布局; 识别第一图中的第一和第二对未连接顶点，分别插入第一和第二冗余边缘，第一冗余边缘和第二冗余边缘分别形成第一连接环路和第二连接环路，每个环路 还包括所述第一图形的至少两个边缘; 计算第一冗余边缘和第二冗余边缘的容差比; 根据其容差比对第一和第二冗余边进行排序; 计算与插入具有最高容差比的第一或第二冗余边缘之一相关联的第一IC布局的产出率变化，以及如果产出率变化较大，则更新第一IC布局以包括具有最高容差比的冗余边缘 比零; 以及计算与插入具有第二高容差比的第一或第二冗余边缘相关联的第一IC布局的产出率变化，并且如果产出率变化为更新，则将第一IC布局更新为包括具有第二高容差比的冗余边缘 大于零。

公开(公告)号：US07917880B2

公开(公告)日：2011-03-29

申请号：US12042978

申请日：2008-03-05

申请人： Wai Kei Mak ,  Wei Chung Chao

发明人： Wai Kei Mak ,  Wei Chung Chao

IPC分类号： G06F17/50 ,  G06F9/455

CPC分类号： G06F17/505 ,  G06F2217/62 ,  G06F2217/78

摘要： A method for reducing power consumption for an integrated circuit comprises the steps of (1) providing (i) a clock tree wherein the clock tree comprises a clock source, a plurality of clock sinks, and a plurality of internal nodes, (ii) the physical locations of the clock source, the clock sinks, and physical location of a gating-signal control logic circuit, (iii) the activity information of the sinks; (2) recursively determining a merging segment set containing merging segments for each internal node and computing switched capacitance of a subtree rooted at each internal node in a bottom up manner, wherein the merging segments have the same signal delay for the clock sinks in a subtree rooted at each internal node; and (3) recursively determining a location for each internal node selected from the merging segment set in a top down manner on a basis that the switched capacitance of a subtree rooted at each internal node is minimum.

摘要翻译： 一种用于降低集成电路的功耗的方法包括以下步骤：（1）提供（i）时钟树，其中时钟树包括时钟源，多个时钟汇和多个内部节点，（ii） 时钟源的物理位置，时钟信宿和门控信号控制逻辑电路的物理位置，（iii）汇点的活动信息; （2）递归地确定包含每个内部节点的合并段的合并段集合，并且以自下而上的方式计算以每个内部节点为根的子树的切换电容，其中合并段具有与子树中的时钟信宿相同的信号延迟 植根于每个内部节点; 并且（3）基于以每个内部节点为根的子树的切换电容为基础，以自顶向下的方式递归地确定从合并段选择的每个内部节点的位置。