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公开(公告)号：US20190284092A1
公开(公告)日：2019-09-19
申请号：US16240750
申请日：2019-01-06
申请人： Sheng-Hsiung Chen
发明人： Sheng-Hsiung Chen
摘要： A method for manufacturing antimicrobial glass includes the steps of: a) providing a glass with alkali metal ions; b) placing the glass in a first oven to perform semi-physical strengthening and dealkalization; and c) placing the glass in a second oven to perform chemical strengthening.
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公开(公告)号：US20120137265A1
公开(公告)日：2012-05-31
申请号：US13289965
申请日：2011-11-04
IPC分类号： G06F17/50
CPC分类号： G06F17/5077
摘要： Multiple level spine routing is disclosed. In some embodiments, in response to receiving a specification of a plurality of nets and a specification of a set of routing tracks available for main spines, a main spine routing track is assigned to each of the plurality of nets based at least in part on a cost function and main spine wires are generated on the assigned main spine routing tracks for each of the plurality of nets.
摘要翻译： 公开了多级脊柱布线。 在一些实施例中，响应于接收到多个网络的规范以及可用于主刺的一组路由路径的规范，主脊线路由轨道至少部分地基于一个主网络路由轨道被分配给多个网络中的每一个网络 成本函数和主脊线在所分配的主脊线路径轨迹上生成，用于多个网络中的每一个。
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公开(公告)号：US07026721B2
公开(公告)日：2006-04-11
申请号：US09755282
申请日：2001-01-08
申请人： Sheng-Hsiung Chen
发明人： Sheng-Hsiung Chen
CPC分类号： H01L24/48 , H01L24/03 , H01L24/05 , H01L24/11 , H01L24/45 , H01L2224/0401 , H01L2224/04042 , H01L2224/05073 , H01L2224/05187 , H01L2224/05557 , H01L2224/05558 , H01L2224/05559 , H01L2224/05624 , H01L2224/13099 , H01L2224/45015 , H01L2224/45124 , H01L2224/45144 , H01L2224/4807 , H01L2224/48458 , H01L2224/4847 , H01L2224/48624 , H01L2224/48724 , H01L2224/48799 , H01L2224/48824 , H01L2224/859 , H01L2924/00011 , H01L2924/01005 , H01L2924/01006 , H01L2924/01007 , H01L2924/01012 , H01L2924/01013 , H01L2924/01014 , H01L2924/01015 , H01L2924/01024 , H01L2924/01029 , H01L2924/01073 , H01L2924/01074 , H01L2924/01079 , H01L2924/014 , H01L2924/04953 , H01L2924/05042 , H01L2924/10253 , H01L2924/13091 , H01L2924/14 , H01L2924/19041 , H01L2924/20753 , H01L2924/351 , H01L2924/00014 , H01L2924/04941 , H01L2924/00 , H01L2924/00015
摘要： This invention relates to a new improved method and structure in the fabricating of aluminum metal pads. The formation special aluminum bond pad metal structures are described which improve adhesion between the tantalum nitride pad barrier layer and the underlying copper pad metallurgy by a special interlocking bond pad structure. It is the object of the present invention to provide a process wherein a special grid of interlocking via structures is placed in between the underlying copper pad metal and the top tantalum nitride pad barrier layer providing improved adhesion to the aluminum pad metal stack structure. This unique contact bond pad structure provides for thermal stress relief, improved wire bond adhesion to the aluminum pad, and prevents peeling during wire bond adhesion tests.
摘要翻译： 本发明涉及铝制金属垫的制造中的新的改进方法和结构。 描述了形成特殊的铝接合焊盘金属结构，其通过特殊的互锁接合焊盘结构提高了氮化钽焊盘阻挡层和下面的铜焊盘冶金之间的粘附性。 本发明的目的是提供一种方法，其中将互锁通孔结构的特殊格栅放置在下面的铜垫金属和顶部的氮化钽衬垫阻挡层之间，从而提供对铝垫金属叠层结构的改进的粘合性。 这种独特的接触焊盘结构提供了热应力释放，改善了与铝焊盘的接合线粘合，并防止了焊线粘附试验期间的剥离。
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公开(公告)号：US06573187B1
公开(公告)日：2003-06-03
申请号：US09378458
申请日：1999-08-20
申请人： Sheng-Hsiung Chen , Ming-Hsing Tsai
发明人： Sheng-Hsiung Chen , Ming-Hsing Tsai
IPC分类号： H01L21302
CPC分类号： H01L21/76835 , H01L21/76807
摘要： A new method is provided for creating a dual damascene structure. Two layers of dielectric are deposited in sequence. The lower layer of dielectric is the via dielectric and is selected such that it has a low etching rate (when compared with the upper layer of dielectric) and results in different volatile gas during the etch of the via. A first photoresist is patterned for the via, the etch for the via etches through both layers of dielectric. A second layer of photoresist is patterned for the trench etch, due to the difference in etch rate between the two layers of dielectric, the trench of the dual damascene structure is etched without further affecting the via etch in the lower layer of dielectric.
摘要翻译： 提供了一种创建双镶嵌结构的新方法。 依次沉积两层电介质。 电介质的下层是通孔电介质，并且被选择为使得其具有低蚀刻速率（当与电介质的上层相比时），并且在蚀刻通孔期间导致不同的挥发性气体。 对于通孔图案化第一光致抗蚀剂，蚀刻通过两个电介质层的通孔蚀刻。 为了沟槽蚀刻，第二层光致抗蚀剂被图案化，由于两层电介质之间的蚀刻速率差异，双镶嵌结构的沟槽被蚀刻，而不会进一步影响电介质的下层中的通孔蚀刻。
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公开(公告)号：US06560862B1
公开(公告)日：2003-05-13
申请号：US09777302
申请日：2001-02-06
申请人： Sheng-Hsiung Chen , Shun Long Chen , Hungtse Lin
发明人： Sheng-Hsiung Chen , Shun Long Chen , Hungtse Lin
IPC分类号： H01R900
CPC分类号： H01L24/05 , H01L23/3192 , H01L23/5226 , H01L24/45 , H01L24/48 , H01L2224/04042 , H01L2224/05073 , H01L2224/05093 , H01L2224/05187 , H01L2224/05624 , H01L2224/45144 , H01L2224/48463 , H01L2224/48624 , H01L2224/48799 , H01L2224/48824 , H01L2924/01012 , H01L2924/01013 , H01L2924/01019 , H01L2924/01022 , H01L2924/01029 , H01L2924/0105 , H01L2924/01079 , H01L2924/04941 , H01L2924/05042 , Y10T29/49147 , Y10T29/49149 , H01L2924/00014 , H01L2924/04953 , H01L2924/00
摘要： A method to fabricate a bonding pad structure including the following steps. A substrate having a top metal layer and a passivation layer overlying the top metal layer is provided. The top metal layer being electrically connected to a lower metal layer by at least one metal via within a metal via area. The substrate includes a low-k dielectric layer at least between the lower metal layer and the top metal layer. The passivation layer is etched within the metal via area to form a trench exposing at least a portion of the top metal layer. A patterned, extended bonding pad is formed over the etched passivation layer and lining the trench. The extended bonding pad having a portion that extends over a peripheral planar area of the substrate adjacent the trench not within the metal via area. A wire bond is bonded to the extended bonding pad at the peripheral planar area portion to form the bonding pad structure.
摘要翻译： 一种制造焊盘结构的方法，包括以下步骤。 提供了具有顶部金属层和覆盖顶部金属层的钝化层的衬底。 顶部金属层通过金属通孔区域内的至少一个金属通孔电连接到下部金属层。 衬底包括至少在下金属层和顶部金属层之间的低k电介质层。 在金属通孔区域内蚀刻钝化层以形成露出顶部金属层的至少一部分的沟槽。 在蚀刻的钝化层之上形成图案化的延伸焊盘，并衬在沟槽上。 所述延伸接合焊盘具有在所述衬底的与所述沟槽相邻的外围平面区域上延伸而不在所述金属通孔区域内的部分。 在周边平面区域部分处将引线键合到延伸焊盘上以形成焊盘结构。
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公开(公告)号：US06303498B1
公开(公告)日：2001-10-16
申请号：US09378497
申请日：1999-08-20
申请人： Sheng-Hsiung Chen , Ming-Hsing Tsai
发明人： Sheng-Hsiung Chen , Ming-Hsing Tsai
IPC分类号： H01L2144
CPC分类号： H01L21/76873 , H01L21/76843
摘要： A new method is provided whereby a copper seed layer is deposited over a barrier layer of TaN. Under the first embodiment of the invention, a doped seed layer is deposited over the barrier layer. Under the second embodiment of the invention a thin layer of metal is deposited over a seed layer of pure copper thereby preventing oxidation of the copper seed layer.
摘要翻译： 提供了一种新的方法，其中铜籽晶层沉积在TaN的阻挡层上。 在本发明的第一实施例中，在阻挡层上沉积掺杂种子层。 在本发明的第二实施例中，在纯铜的种子层上沉积薄层金属，从而防止铜籽晶层的氧化。
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7.发明授权公开(公告)号：US06235637B1
公开(公告)日：2001-05-22
申请号：US09396518
申请日：1999-09-15
申请人： Sheng-Hsiung Chen , Ming-Hsing Tsai
发明人： Sheng-Hsiung Chen , Ming-Hsing Tsai
IPC分类号： H01L21311
CPC分类号： H01L23/544 , H01L2223/54493 , H01L2924/0002 , H01L2924/00
摘要： A method for marking a semiconductor wafer without inducing flat edge particles, using a laser scribing technique. The process begins by providing a semiconductor wafer having a marking area with a silicon top layer. The semiconductor wafer is coated with a photoresist layer. A volume of the photoresist layer and a volume of silicon top layer are removed corresponding to the intended marking. Optionally, the marking pattern can be further etched into the silicon top layer by anisotropic etching, using the photoresist layer as an etching mask. In another option, the laser scribing process can be set to scribe the marking pattern in the photoresist layer without scribing the silicon top layer. The marking pattern can then be anisotropically etched into the silicon top layer, using the photoresist layer as an etching mask. Alternatively, the photoresist layer can be patterned to form an opening in the photoresist layer over a marking area, thereby exposing the silicon top layer. The silicon top layer is then marked using a laser scribing technique, and the photoresist layer prevents contamination of the device areas of the wafer by the silicon particles generated by the laser scribing technique.
摘要翻译： 使用激光划线技术来标记半导体晶片而不引起平坦边缘颗粒的方法。 该过程开始于提供具有带硅顶层的标记区域的半导体晶片。 半导体晶片被涂覆有光致抗蚀剂层。 根据预期的标记去除光致抗蚀剂层的体积和硅顶层的体积。 可选地，使用光致抗蚀剂层作为蚀刻掩模，可以通过各向异性蚀刻将标记图案进一步蚀刻到硅顶层中。 在另一种选择中，可以设置激光划线工艺以划刻光致抗蚀剂层中的标记图案，而无需划线硅顶层。 然后可以使用光致抗蚀剂层作为蚀刻掩模将标记图案各向异性地蚀刻到硅顶层中。 或者，光致抗蚀剂层可以被图案化以在标记区域上在光致抗蚀剂层中形成开口，从而暴露硅顶层。 然后使用激光划线技术标记硅顶层，并且光致抗蚀剂层防止由激光划线技术产生的硅颗粒对晶片的器件区域的污染。
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公开(公告)号：US08959473B2
公开(公告)日：2015-02-17
申请号：US13289965
申请日：2011-11-04
IPC分类号： G06F17/50
CPC分类号： G06F17/5077
摘要： Multiple level spine routing is disclosed. In some embodiments, in response to receiving a specification of a plurality of nets and a specification of a set of routing tracks available for main spines, a main spine routing track is assigned to each of the plurality of nets based at least in part on a cost function and main spine wires are generated on the assigned main spine routing tracks for each of the plurality of nets.
摘要翻译： 公开了多级脊柱布线。 在一些实施例中，响应于接收到多个网络的规范以及可用于主刺的一组路由路径的规范，主脊线路由轨道至少部分地基于一个主网络路由轨道被分配给多个网络中的每一个网络 成本函数和主脊线在所分配的主脊线路径轨迹上生成，用于多个网络中的每一个。
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公开(公告)号：US08683417B2
公开(公告)日：2014-03-25
申请号：US13289963
申请日：2011-11-04
IPC分类号： G06F17/50
CPC分类号： G06F17/5077
摘要： Multiple level spine routing is disclosed. In some embodiments, in response to receiving a specification of a net comprising a set of pins, a first wire for routing the net is generated, the set of pins comprising the net is partitioned into one or more groups based at least in part on a cost function, a second wire that connects to the first wire is generated for each group of the net, and a third wire that connects each pin to the second wire of its group is generated for each pin of each group of the net.
摘要翻译： 公开了多级脊柱布线。 在一些实施例中，响应于接收到包括一组引脚的网络的规范，产生用于布线网络的第一线，包括网的引脚组被至少部分地基于一个或多个 为每组网络生成连接到第一线的第二线，并且为每组网的每个针产生将每个引脚连接到其组的第二线的第三线。
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公开(公告)号：US08561002B2
公开(公告)日：2013-10-15
申请号：US13289963
申请日：2011-11-04
IPC分类号： G06F17/50
摘要： Multiple level spine routing is disclosed. In some embodiments, in response to receiving a specification of a net comprising a set of pins, a first wire for routing the net is generated, the set of pins comprising the net is partitioned into one or more groups based at least in part on a cost function, a second wire that connects to the first wire is generated for each group of the net, and a third wire that connects each pin to the second wire of its group is generated for each pin of each group of the net.
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