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公开(公告)号：US4759037A
公开(公告)日：1988-07-19
申请号：US856397
申请日：1986-04-28
Applicant: Walter Debus, Jr. , Peter D. Karabinis
Inventor： Walter Debus, Jr. , Peter D. Karabinis
CPC classification number: H04L27/01
Abstract: A technique is disclosed for equalizing an incoming signal including quadrature-related carrier signals by forming the product of the incoming signal at at least one prescribed time and only one real-valued coefficient associated with each time. In one embodiment of the present invention, the equalized incoming signal is demodulated into a first pair of component signals. At least one of these component signals is then used to generate each coefficient. In another embodiment of the present invention, each coefficient is generated in response to at least one of the component signals in the first pair along with a second pair of component signals which are formed by demodulating the incoming signal. This technique can be advantageously adapted to incorporate a number of coefficient updating algorithms and is suitable for use in a number of modulation formats.
Abstract translation: 公开了一种技术，用于通过在至少一个规定时间形成输入信号的乘积和仅与每次相关联的一个实值系数来均衡包括正交相关载波信号的输入信号。 在本发明的一个实施例中，均衡的输入信号被解调成第一对分量信号。 然后使用这些分量信号中的至少一个来产生每个系数。 在本发明的另一个实施例中，响应于第一对中的分量信号中的至少一个以及通过解调输入信号形成的第二对分量信号而产生每个系数。 该技术可以有利地适用于并入多个系数更新算法，并且适用于多种调制格式。
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公开(公告)号：US4727534A
公开(公告)日：1988-02-23
申请号：US899411
申请日：1986-08-19
Applicant: Walter Debus, Jr. , Mohsen Kavehrad
Inventor： Walter Debus, Jr. , Mohsen Kavehrad
CPC classification number: H04L7/0062 , H04B7/002 , H04J15/00 , H04L27/38
Abstract: A technique is disclosed for improving the recovery of data signals transmitted on orthogonally polarized carrier signals by creating redundancy with respect to timing and carrier information. In the receiver, the carrier and timing recovery circuitry, which controls the recovery of the data signals from the incoming orthogonally polarized carrier signals, operate in response to a selected one of the carrier signals or at least one data signal recovered from this selected carrier signal. This selection is based on an examination of the data signals recovered from each of the orthogonally polarized carrier signals. Use of the described technique advantageously lessens the possibility of the carrier and timing recovery circuits losing synchronous operation during fading as it is less likely that a fade will simultaneously affect both orthogonally polarized carrier signals. As a result, data signal recovery is improved.
Abstract translation: 公开了一种用于通过相对于定时和载波信息产生冗余来改善在正交极化载波信号上传输的数据信号的恢复的技术。 在接收机中，控制从输入的正交极化载波信号恢复数据信号的载波和定时恢复电路响应于所选择的一个载波信号或从该选择的载波信号恢复的至少一个数据信号而工作 。 该选择基于从每个正交极化载波信号恢复的数据信号的检查。 使用所描述的技术有利地减少了在衰落期间载波和定时恢复电路失去同步操作的可能性，因为衰落不太可能同时影响正交极化载波信号。 结果，数据信号恢复得到改善。
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3.发明授权
公开(公告)号：US4550415A
公开(公告)日：1985-10-29
申请号：US552415
申请日：1983-11-16
Applicant: Walter Debus, Jr. , Curtis H. Siller
Inventor： Walter Debus, Jr. , Curtis H. Siller
CPC classification number: H04L25/03044
Abstract: A fractionally spaced adaptive equalizer is disclosed wherein the coefficients (C.sub.-2 to C.sub.+2) are updated synchronously by an integral -T error circuit (40) and alternately by a fractional =T error circuit (48). This arrangement features a single unique minimum for the adaptive structure thereby preventing the coefficient drift to very large values so coefficient tap leakage is not required to minimize coefficient values. The adaptive characteristic is well suited for linearly dispersive channels, such as exhibited during terrestrial radio transmission during tropospheric multipath propagation. The inventive principles are broadly applicable to any of the well known algorithms for adapting digital filters. A configuration of fractionally spaced equalizers (70.sub.1 -70.sub.4) provides the benefits of Nyquist-rate coefficient updating for a dual rail quadrature amplitude modulated (QAM) signal application.
Abstract translation: 公开了一种分数间隔的自适应均衡器，其中系数（C-2至C + 2）由积分-T误差电路（40）同步地更新，并且交替地由小数= T误差电路（48）更新。 这种布置对于自适应结构具有单一唯一的最小值，从而防止系数漂移到非常大的值，因此不需要系数抽头泄漏以使系数值最小化。 自适应特性非常适合于线性色散信道，例如在对流层多径传播期间的地面无线电传输期间展示的。 本发明的原理广泛地适用于任何适用于数字滤波器的众所周知的算法。 分数间隔均衡器（701-704）的配置为双轨正交幅度调制（QAM）信号应用提供奈奎斯特率系数更新的好处。
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公开(公告)号：US4831382A
公开(公告)日：1989-05-16
申请号：US53939
申请日：1987-05-26
Applicant: Walter Debus, Jr. , Gerhard W. Stenger
Inventor： Walter Debus, Jr. , Gerhard W. Stenger
CPC classification number: H03M1/182
Abstract: An analog-to-digital converter having adaptable quantizing levels which compensate for unintended variations in the analog input signal amplitude. Variations in the amplitude range over which the quantizing levels extend is determined from an examination of preselected bits of the analog-to-digital converter output.
Abstract translation: 具有适应性量化电平的模拟 - 数字转换器，其补偿模拟输入信号幅度的非预期变化。 通过检查模数转换器输出的预选位来确定量化电平延伸的幅度范围的变化。
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Patent Agency Ranking
公开(公告)号：US4627080A
公开(公告)日：1986-12-02
申请号：US674312
申请日：1984-11-23
Applicant: Walter Debus, Jr.
Inventor： Walter Debus, Jr.
CPC classification number: H04L7/0062 , H04L7/0083
Abstract: An adaptive timing technique is disclosed for adjusting the sampling times of a received digital signal for fewer regeneration errors. In accordance with the disclosed technique, a sequence of digital signal samples is formed and an error signal is generated by comparing a selected sample in the sequence to a threshold. The sampling times of subsequently formed samples are then altered in response to the sample sequence and error signal only when the sample values in the sequence are successively increasing or decreasing.
Abstract translation: 公开了一种自适应定时技术，用于调整接收的数字信号的采样时间以减少再生误差。 根据所公开的技术，形成数字信号样本序列，并通过将序列中的选定样本与阈值进行比较来产生误差信号。 随后随后形成的样本的采样时间随着样品序列和误差信号的响应而改变，只有当序列中的样品值连续增加或减少时。
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6.发明授权Adaptive equalizer utilizing a plurality of multiplier-accumulator devices 失效利用多个乘法器 - 累加器装置的自适应均衡器
公开(公告)号：US4773034A
公开(公告)日：1988-09-20
申请号：US732403
申请日：1985-05-09
Applicant: Walter Debus, Jr.
Inventor： Walter Debus, Jr.
CPC classification number: H03H21/0012
Abstract: Each multiply-accumulate device, in an adaptive equalizer, multiplies each input signal sample by an associated coefficient in an ensemble, stores the result and periodically outputs the accumulated results as the equalized input signal. A rotating coefficient register in the adaptive equalizer successively associates each coefficient in the ensemble with a different multiply-accumulate device. Coefficient update circuitry is also provided which periodically updates the coefficients in the ensemble so as to optimize equalizer performance.
Abstract translation: 每个乘法累加装置在自适应均衡器中，将每个输入信号样本乘以一个组合中的相关系数，存储结果并周期性地输出累积结果作为均衡输入信号。 自适应均衡器中的旋转系数寄存器将集合中的每个系数与不同的乘法累加装置相关联。 还提供系数更新电路，其周期性地更新集合中的系数，以便优化均衡器性能。
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7.发明授权
公开(公告)号：US4759039A
公开(公告)日：1988-07-19
申请号：US920367
申请日：1986-10-20
Applicant: Walter Debus, Jr. , Howard C. Reeve, III , Curtis A. Siller, Jr.
Inventor： Walter Debus, Jr. , Howard C. Reeve, III , Curtis A. Siller, Jr.
CPC classification number: H04L27/363 , H04L27/3881
Abstract: A technique is presented for simplifying the recovery of two synchronous data signals having a common symbol rate after each signal has respectively modulated a different one of a pair of quadrature-related carrier signals. In the transmitter, the data signal which modulates one of the quadrature-related carrier signals is delayed relative to the data signal which modulates the other quadrature-related carrier signal. This delay is related to an IF frequency chosen at the receiver. After passing through a noisy transmission channel, the quadrature-related carrier signals are coupled in the receiver to a serial combination of an equalizer and analog-to-digital converter. This combination outputs multiple, substantially distortion-free samples of the data signals each symbol interval. The two data signals are then recovered by selecting a subset of the samples provided each symbol interval.
Abstract translation: 提出了一种技术，用于在每个信号分别调制一对正交相关载波信号中的不同的一个之后，简化具有公共符号速率的两个同步数据信号的恢复。 在发射机中，调制正交相关载波信号之一的数据信号相对于调制另一正交相关载波信号的数据信号被延迟。 该延迟与在接收机处选择的IF频率有关。 在通过噪声传输信道之后，正交相关载波信号在接收机中耦合到均衡器和模数转换器的串行组合。 该组合输出每个符号间隔的数据信号的多个基本上无失真的采样。 然后通过选择每个符号间隔提供的样本的子集来恢复两个数据信号。
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8.发明授权
公开(公告)号：US4736389A
公开(公告)日：1988-04-05
申请号：US892232
申请日：1986-08-04
Applicant: Walter Debus, Jr. , Howard C. Reeve, III , Curtis A. Siller, Jr.
Inventor： Walter Debus, Jr. , Howard C. Reeve, III , Curtis A. Siller, Jr.
CPC classification number: H04L27/365 , H04L25/03133 , H04L27/04 , H04L27/36
Abstract: A technique for digitally synthesizing the amplitude modulation of one or more carrier signals with a random digital data signal is disclosed. Pursuant to the present invention, a memory unit is addressed by a plurality of binary coded digital symbols in the data signal. For each address, at least two digital representations are read out. Each representation corresponds to a different sample of the carrier signals which has been amplitude modulated by a composite of the spectrally shaped data signal. The disclosed technique can be adapted to synthesize a variety of modulation formats, and can provide compensation for fixed in-rail and cross-rail distortions.
Abstract translation: 公开了一种用随机数字数据信号数字合成一个或多个载波信号的幅度调制的技术。 根据本发明，存储器单元由数据信号中的多个二进制编码数字符号寻址。 对于每个地址，读出至少两个数字表示。 每个表示对应于通过频谱形状的数据信号的复合振幅调制的载波信号的不同采样。 所公开的技术可以适合于综合各种调制格式，并且可以为固定的轨内和轨道的变形提供补偿。
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9.发明授权
公开(公告)号：US4710891A
公开(公告)日：1987-12-01
申请号：US517803
申请日：1983-07-27
Applicant: Walter Debus, Jr. , Thomas L. Osborne , Curtis A. Siller, Jr.
Inventor： Walter Debus, Jr. , Thomas L. Osborne , Curtis A. Siller, Jr.
IPC: H04L25/49 , H03H17/02 , H04L25/497 , G06F1/02
CPC classification number: H04L25/497
Abstract: A digital synthesis technique provides pulse shaping in accordance with predetermined time domain and frequency domain constraints. In the technique, the informational content of a binary bit stream is used by an access circuit (12) to form address words for accessing a read-only-memory (13). The digital representations stored in the ROM (13) represent a superposition of temporally-displaced truncated impulse time functions, each weighted by the discrete transmission symbol levels of the analog output signal. The digital representations from two ROMs (13-1 and 13-2) are toggled by a sequencng circuit. In other embodiments of the invention, different memory arrangements ranging from a signal ROM (142) to an array of ROMS (163-1 through 163-3 and 164-1 through 164-3) are respectively used to decrease circuit complexity. In a digital radio transmission application of the technique, this arrangement is economical, readily reproducible and stable since it obviates the need for conventional complex analog filters.
Abstract translation: 数字合成技术根据预定的时域和频域约束提供脉冲整形。 在该技术中，由访问电路（12）使用二进制比特流的信息内容来形成访问只读存储器（13）的地址字。 存储在ROM（13）中的数字表示表示时间偏移截断的脉冲时间函数的叠加，每个功能由模拟输出信号的离散传输符号电平加权。 来自两个ROM（13-1和13-2）的数字表示由顺序电路切换。 在本发明的其他实施例中，分别使用从信号ROM（142）到ROMS阵列（163-1至163-3和164-1至164-3）的不同存储器配置来降低电路复杂度。 在该技术的数字无线电传输应用中，这种布置是经济的，易于再现的和稳定的，因为它消除了对常规复杂模拟滤波器的需要。
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