公开(公告)号：US20120049332A1

公开(公告)日：2012-03-01

申请号：US13181278

申请日：2011-07-12

申请人： Jen-Chuan Chen ,  Hui-Shan Chang ,  Wen-Hsiung Chang ,  Wei-Nung Chang

发明人： Jen-Chuan Chen ,  Hui-Shan Chang ,  Wen-Hsiung Chang ,  Wei-Nung Chang

IPC分类号： H01L23/58 ,  H01L21/82

CPC分类号： H01L25/0657 ,  H01L24/97 ,  H01L2224/16225 ,  H01L2224/97 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06548 ,  H01L2225/06572 ,  H01L2924/01033 ,  H01L2924/01075 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/181 ,  H01L2224/81 ,  H01L2924/00

摘要： A semiconductor package and method for making the same are provided, wherein a lower chip having a plurality of conductive structures is bonded to an upper surface of a package substrate and a plurality of matrix walls are formed on the upper surface for surrounding the lower chip, such that an overcoat layer covering the matrix walls and the lower chip can be approximately removed after performing a grinding process to the lower chip to expose a plurality of conductive vias of the lower chip. The cleaning step for removing the residue of overcoat layer can be omitted, and the processing yield and the processing efficiency can be improved. The semiconductor package and the method is particularly suitable for stacking a large dimensional upper chip on a relatively small dimensional lower chip.

摘要翻译： 提供一种半导体封装及其制造方法，其中具有多个导电结构的下部芯片被结合到封装衬底的上表面，并且在上表面上形成多个矩阵壁以围绕下部芯片， 使得覆盖矩阵壁和下部芯片的外涂层可以在对下部芯片进行研磨处理之后大致去除以暴露下部芯片的多个导电通孔。 可以省略除去外涂层残渣的清洗工序，可以提高加工量和加工效率。 该半导体封装和该方法特别适用于在相对较小尺寸的下部芯片上堆叠大尺寸上部芯片。