公开(公告)号：US20050040864A1

公开(公告)日：2005-02-24

申请号：US10604799

申请日：2003-08-18

申请人： Westerfield Ficken ,  Louis Hsu ,  James Mason ,  Phil Murfet

发明人： Westerfield Ficken ,  Louis Hsu ,  James Mason ,  Phil Murfet

IPC分类号： G05F1/10 ,  H03K5/08 ,  H03K5/19 ,  H03K5/22 ,  H04L25/02 ,  H04L25/08

CPC分类号： H03K5/19 ,  H03K5/08 ,  H04L25/0272 ,  H04L25/085

摘要： An apparatus and method is provided for detecting loss of differential signal carried by a pair of differential signal lines. According to the method, a common mode level is detected from voltages on the pair of differential signal lines. A threshold level is generated, referenced to the detected common mode level. A signal level is generated from the voltages on the pair of differential signal lines, the signal level being averaged over a first period of time. From the threshold level and the detected common mode level a reference level is generated, the reference level being averaged over a second period of time longer than then the first period of time. The signal level is compared to the reference level to determine if a signal is present on the pair of differential signal lines.

摘要翻译： 提供一种用于检测由一对差分信号线携带的差分信号的损耗的装置和方法。 根据该方法，从该对差分信号线上的电压检测共模电平。 产生阈值电平，参考检测到的共模电平。 信号电平由一对差分信号线上的电压产生，信号电平在第一时间段内被平均化。 从阈值电平和检测到的共模电平产生参考电平，在比第一时间段长的第二时间段内平均参考电平。 将信号电平与参考电平进行比较，以确定信号对是否存在于该对差分信号线上。

公开(公告)号：US20080012642A1

公开(公告)日：2008-01-17

申请号：US11417626

申请日：2006-05-04

申请人： Hayden Cranford ,  Westerfield Ficken ,  David Freitas ,  Joseph Stevens

发明人： Hayden Cranford ,  Westerfield Ficken ,  David Freitas ,  Joseph Stevens

IPC分类号： H03F3/45

CPC分类号： H03F3/45475 ,  H03F1/52 ,  H03F3/45973 ,  H03F2203/45078 ,  H03F2203/45431 ,  H03F2203/45541 ,  H03F2203/45561 ,  H03F2203/45588

摘要： A circuit device and method for designing a serial link receiver, which accommodates a wide input voltage range and provides tolerance to high termination voltages. The receiver is designed with a pair of RC networks connected inline between the input and the preamplifier and a common mode feedback loop, which monitors shifts in the common mode voltage and adjusts the inputs provided to the preamplifier. The circuit device maintains a flat bandwidth to accommodate all signaling rates.

摘要翻译： 一种用于设计串行链路接收机的电路装置和方法，其适应宽的输入电压范围并且提供对高终端电压的容限。 接收机设计有一对连接在输入和前置放大器之间的RC网络和一个共模反馈环路，它监控共模电压的变化并调整提供给前置放大器的输入。 电路设备保持平坦的带宽以适应所有信令速率。

公开(公告)号：US20050281355A1

公开(公告)日：2005-12-22

申请号：US10873672

申请日：2004-06-22

申请人： Hayden Cranford ,  Westerfield Ficken

发明人： Hayden Cranford ,  Westerfield Ficken

IPC分类号： H04L27/06 ,  H04L27/08

CPC分类号： H04L27/06 ,  H04L27/08

摘要： Methods, systems, and media to time-share the signal detection between reference voltages for a data transmission are contemplated. Embodiments include a time-sharing detector that is designed to enable comparison of a first reference voltage and a second reference voltage against the serial data transmission in a specified pattern. In many embodiments, the pattern is pre-defined and, in some embodiments, the pattern includes an overlap period. During the overlap period both the first and the second reference voltages are compared with the data transmission to determine if valid data can be detected. Upon detecting a valid bit based upon one of the reference voltages, an output signal is generated to indicate that the data transmission includes a valid data signal. Advantageously, alternating between the comparisons can reduce power consumption. In many embodiments, the power reduction can be, for example, 50%, depending upon the specified pattern.

摘要翻译： 考虑用于数据传输的参考电压之间的时间共享信号检测的方法，系统和媒体。 实施例包括分时检测器，其被设计为能够以指定的模式与第一参考电压和第二参考电压相对于串行数据传输进行比较。 在许多实施例中，图案是预定义的，并且在一些实施例中，图案包括重叠周期。 在重叠期间，将第一和第二参考电压与数据传输进行比较，以确定是否可以检测有效数据。 在基于参考电压之一检测到有效位时，产生输出信号以指示数据传输包括有效数据信号。 有利地，比较之间的交替可以降低功耗。 在许多实施例中，取决于指定的模式，功率降低可以是例如50％。

公开(公告)号：US20050058231A1

公开(公告)日：2005-03-17

申请号：US10665235

申请日：2003-09-17

申请人： Hayden Cranford ,  Westerfield Ficken ,  Wentai Liu

发明人： Hayden Cranford ,  Westerfield Ficken ,  Wentai Liu

IPC分类号： H04L1/00 ,  H04L25/03

CPC分类号： H04L25/03133

摘要： A method and system for is disclosed for reducing intersymbol interference in a stream of data bits to be transmitted over a transmission medium. Aspects of the present invention include a phase delayed clock generated from a reference clock that produces an edge on sub-bit boundaries; and a digital filter coupled to the phase delayed clock for performing equalization on the data bits, wherein the phase delayed clock causes the digital filter to perform partial clock switching, such that equalization is performed on the data bits on-sub-bit boundaries.

摘要翻译： 公开了一种用于减少要在传输介质上传输的数据位流中的符号间干扰的方法和系统。 本发明的方面包括从产生子位边界边缘的参考时钟产生的相位延迟时钟; 以及耦合到所述相位延迟时钟的数字滤波器，用于对所述数据位执行均衡，其中所述相位延迟时钟使所述数字滤波器执行部分时钟切换，使得对所述数据位在子位边界执行均衡。

公开(公告)号：US20070035342A1

公开(公告)日：2007-02-15

申请号：US11203860

申请日：2005-08-15

申请人： Minhan Chen ,  Westerfield Ficken ,  Louis Hsu ,  Steven Zier

发明人： Minhan Chen ,  Westerfield Ficken ,  Louis Hsu ,  Steven Zier

IPC分类号： H03F3/45

CPC分类号： H03F3/45197 ,  H03F2203/45424 ,  H03F2203/45431 ,  H03F2203/45488 ,  H03F2203/45646

摘要： Offset voltages in differential amplifiers are minimized by controlling compensation currents through the load impedances of the amplifiers. The currents are varied while sensing the polarity of the offset voltage. When the polarity changes, the current values are latched to keep the offset voltage at a minimum.