公开(公告)号：US4393509A

公开(公告)日：1983-07-12

申请号：US252737

申请日：1981-04-10

申请人： George Merkel ,  William D. Scharf

发明人： George Merkel ,  William D. Scharf

IPC分类号： F41A33/00 ,  G21C17/00 ,  G21G3/04

CPC分类号： F41A33/00 ,  G21C17/001

摘要： A method and apparatus for simulating, in conjunction with a source of ionizing radiation, intense pulsed electromagnetic fields and time varying conductivity caused by the gamma radiation associated with a nuclear detonation. An enclosed space, including the source of ionizing radiation is separated into three spaces, each space separated from the adjacent space by a gas impermeable, radiation permeable barrier. A guided wave structure, pulsed with high voltage pulses in conjunction with the firing of the source of ionization radiation is disposed adjacent to the barrier separating two of the spaces. A gas handling system is provided to introduce a selected non-ionizing gas and a selected ionizing gas into the spaces on either side of the barrier adjacent to the guided wave structure.

摘要翻译： 一种用于模拟与电离辐射源相关的强脉冲电磁场​​和由与核爆炸相关联的伽马辐射引起的时变电导率的方法和装置。 包括电离辐射源的封闭空间被分离成三个空间，每个空间通过不透气的可辐射屏障与相邻的空间隔开。 与电离辐射源的点火相结合的高电压脉冲脉冲的导波结构设置在隔离两个空间的屏障附近。 提供了一种气体处理系统，用于将所选择的非电离气体和选定的电离气体引入与导波结构相邻的阻挡层两侧的空间中。

公开(公告)号：US07831653B2

公开(公告)日：2010-11-09

申请号：US10318792

申请日：2002-12-13

申请人： George Wayne Nation ,  Gary Scott Delp ,  William D. Scharf ,  Narayanan Raman ,  John N. Fryar, III ,  Majid Bemanian

发明人： George Wayne Nation ,  Gary Scott Delp ,  William D. Scharf ,  Narayanan Raman ,  John N. Fryar, III ,  Majid Bemanian

IPC分类号： G06F15/16

CPC分类号： H04L69/12

摘要： A partially manufactured semiconductor chip comprising a slice and a number of shells is a template for a communication and networking chip. The slice has a number of I/O ports, blocks, and PHYs. The hardmac PHYs are established to correspond to a high speed data transmission protocol. The interior of the template comprises logic gate arrays and configurable memory. Once particular protocols of data receipt and transmission are selected, the logic gate arrays and configurable memory can be programmed and otherwise configured to develop protocol layers for data networking and communication.

摘要翻译： 包括片和多个壳的部分制造的半导体芯片是用于通信和网络芯片的模板。 该片具有多个I / O端口，块和PHY。 硬件PHY被建立为对应于高速数据传输协议。 模板的内部包括逻辑门阵列和可配置存储器。 一旦选择了数据接收和传输的特定协议，逻辑门阵列和可配置存储器可以被编程，否则被配置为开发用于数据联网和通信的协议层。

公开(公告)号：US07185301B2

公开(公告)日：2007-02-27

申请号：US10819254

申请日：2004-04-06

申请人： Hong Hao ,  Keven Hui ,  William D. Scharf

发明人： Hong Hao ,  Keven Hui ,  William D. Scharf

IPC分类号： G06F17/50

CPC分类号： G11C5/025 ,  G06F17/505 ,  G06F2217/62 ,  G06F2217/84 ,  H03K5/135

摘要： The present invention is a method and apparatus for implementing a source synchronous interface in a platform using a Generic Source Synchronous Interface (GSSI) infrastructure. The GSSI infrastructure includes the GSSI bit slices and clock management system. The GSSI bit slice includes balanced cells and bit delay elements, and may be placed either within or close to IO buffers. The GSSI clock management system includes strategically placed frame delay elements with automatic on-chip calibration and control to satisfy various clock-data phase relationships. The GSSI methodology shows how different SSIs may be constructed by combining the common GSSI architecture with unique metal layer configurations. The GSSI architecture solves a critical challenge for platform-based design such as RapidChip™ and the like. The GSSI approach introduces a completely new way to implement various SSIs based on a common minimally diffused GSSI bit slice and clock management infrastructure. This enables one slice of a platform family to be used for many applications, removing the need to provide different slices with different diffused hard macros for different applications.

摘要翻译： 本发明是一种使用通用源同步接口（GSSI）基础设施在平台中实现源同步接口的方法和装置。 GSSI基础设施包括GSSI位片和时钟管理系统。 GSSI位片包括平衡单元和位延迟元件，并且可以放置在IO缓冲器内或靠近IO缓冲器中。 GSSI时钟管理系统包括具有自动片内校准和控制的策略性放置的帧延迟元件，以满足各种时钟数据相位关系。 GSSI方法显示了如何通过将普通GSSI架构与独特的金属层配置相结合来构建不同的SSI。 GSSI架构解决了基于平台的设计（如RapidChip™等）的关键挑战。 GSSI方法引入了一种全新的方式来实现基于通用的最小扩散GSSI位片和时钟管理基础设施的各种SSI。 这使得平台系列的一个切片可用于许多应用，消除了为不同应用提供具有不同扩散硬宏的不同切片的需要。

公开(公告)号：US06934597B1

公开(公告)日：2005-08-23

申请号：US10106432

申请日：2002-03-26

申请人： Majid Bemanian ,  William D. Scharf

发明人： Majid Bemanian ,  William D. Scharf

IPC分类号： G06F15/78 ,  G06F19/00

CPC分类号： G06F15/7867

摘要： An integrated circuit (IC) and a method of manufacturing an integrated circuit suited for a particular application. In one embodiment, the IC includes: (1) at least two interfaces, (2) a programmable gate array (PGA) coupled to the at least two interfaces for communicating data therebetween and, optionally (3) a field-programmable gate array (FPGA) coupled to and configured to cooperate with the PGA to adapt the IC to a particular surrounding environment.

摘要翻译： 一种集成电路（IC）和一种制造适用于特定应用的集成电路的方法。 在一个实施例中，IC包括：（1）至少两个接口，（2）耦合到所述至少两个接口的可编程门阵列（PGA），用于在其间传送数据;以及可选地（3）现场可编程门阵列 FPGA），其耦合并配置成与PGA协作以使IC适应于特定的周围环境。

公开(公告)号：US06904586B1

公开(公告)日：2005-06-07

申请号：US10105579

申请日：2002-03-25

申请人： Majid Bemanian ,  William D. Scharf ,  Bruce L. Entin

发明人： Majid Bemanian ,  William D. Scharf ,  Bruce L. Entin

IPC分类号： G06F15/78 ,  G06F17/50

CPC分类号： G06F17/5054 ,  G06F15/7867

摘要： An integrated circuit (IC) and a method of manufacturing an integrated circuit suited for a particular application. In one embodiment, the IC includes at least two interfaces, a field-programmable gate array (FPGA) and a programmable gate array (PGA). The FPGA has a configuration memory associated therewith and is coupled to the at least two interfaces for communicating data therebetween. The PGA is coupled to and configured to cooperate with the FPGA to adapt the IC to a particular surrounding environment.

摘要翻译： 一种集成电路（IC）和一种制造适用于特定应用的集成电路的方法。 在一个实施例中，IC包括至少两个接口，现场可编程门阵列（FPGA）和可编程门阵列（PGA）。 FPGA具有与其相关联的配置存储器，并且耦合到至少两个接口以在其间传送数据。 PGA被耦合到并配置成与FPGA配合以使IC适应特定的周围环境。